Design And Accomplishment Of The DDR SDRAM Controller Based On Network Processor

The memory storage plays a critical importance on the performance of the widely used digital system, one of the key device deciding the performance of the system. Besides in the computer system, the DDR SDRAM memory is increasingly used in the embedded system and SoC system. More and more SoC system chips integrate DDR interface unit, high in speed, large in storage and reliable in performance, the DDR SDRAM memory become more and more popular.This paper mainly introduced the design and the accomplishment of the DDR SDRAM controller based on Network Processor. Network Processor is used to do data processing and forwarding as a high-speed programmable processor. The slowly SDRAM accessing speed has become a bottleneck in enhancing the performance of the whole network-processor system. Thus, the accessing speed of the DDR SDRAM controller is crucial to the whole system. In order to achieve the conversion of data between external bus master and memory, it uses AMBA bus protocol-based, through AMBA logical interface to send commands, addresses and data.The DDR SDRAM controller is divided into several small modules using the top-down design method in this paper. The design of the DDR address decode module, clock generated module, data path module, the control logical module, counter module and user interface module is complished by the language of verilog HDL and the functions are also simulated and verified on the Xilinx ISE platform. At last the DDR SDRAM controller can successfully visit the external DDR SDRAM storage units based on the FPGA hardware platform.