The Research On Verification Method Of SDRAM Controller Based On UVM

With the rapid development of integrated circuit technology,the market demand for electronic equipment tends to be faster and smaller.Although the cost and time consumed in the design and production of integrated circuits are decreasing,it is especially important to how to ensure the reliable implementation of chip functions in view of the increasing complexity of chips.Therefore,it takes more time to verify the function of the chip,which puts forward certain requirements for the verification technology and methodology.SDRAM controller is an indispensable design for controlling SDRAM's normal work.For the engineering projects with SDRAM and SDRAM controller,it is very important to ensure the correct functional design of SDRAM controller through functional verification.It is very difficult to verify all cases about SDRAM controller by using the traditional directional verification method,and it is inevitable that unexpected loopholes will be ignored.Based on System Verilog language UVM(universal verification methodology,general verification methodology)as a new generation of verification methodology,it absorbs the advantages of OVM,VMM and other validation methods,therefore it can produce a constrained random excitation signal.And it can automatically collect function coverage and analyze the validation results and effectively find defects in the design.In the verification of SDRAM controller,uvm verification methodology can more effectively find defects in the design and greatly shorten the verification time.Through participating in the actual SOC chip project,a UVM verification platform is built for SDRAM controller modules used in the project and carries out a more comprehensive module-level verification so as to make the module function realization conform to the design specifications as much as possible in this article.Firstly,the basic theory of functional verification are analyzed in this article,and the verification platform,verification process and coverage type are studied.Secondly,the methodology of UVM verification is put forward to solve the problems faced by current verification,and the structure and main characteristics of UVM verification platform are analyzed.Afterwards,according to the functional architecture and application environment of SDRAM controller module,the principle of SDRAM memory and the function of SDRAM controller sub-module are studied.The external interface signal,working flow and parameterconfiguration of SDRAM controller module are Analyzed;Verification points are Analyzed and extracted according to the corresponding function and timing characteristics of the module;Thirdly,the overall architecture of SDRAM controller UVM verification platform is analyzed.The uvm verification platform was built through writing and connecting of functional codes of each components in the architecture.Finally,write a test case and start the verification platform for simulation and verification.The simulation and verification work in this article is done by using NC-sim simulation tool under Linux environment.the module is verified through the combination of directional excitation and random excitation.In the simulation process,the typical function simulation waveform of SDRAM controller is analyzed.Through the collection of emulator coverage information,97 % code coverage and 100 % function coverage were finally achieved,which achieved the expected goal.The verification results show that using UVM verification methodology to verify SDRAM controller functions is efficient and complete.