Front-end Design Of An AMBA4 Compliant DDRn SDRAM Controller

There is an increasing number of consumer electronics devices (such as PSP, iPhone, iPAD, digital cameras or GPS devices) which provide higher performance graphics and video capabilities require more, faster and lower power consumption DRAM memory. In the field of signal processing, high efficiency network, and high definition audio/video, memory bandwidth has increasingly become a bottleneck, especially in multi-core SoC designs. Therefore, the increased memory bandwidth is a key factor in improving the system performance.DDRn SDRAM can transfer data at both rising and falling edges of the I/O clock. And it is an improvement over SDR SDRAM. The primary benefit of DDRn SDRAM is the ability to transfer at twice the data, thus enabling higher data transfer rates and higher peak rates than earlier memory technologies. The increased memory bandwidth can help solve the increasingly severe memory bottleneck. The AMBA was introduced by ARM Ltd in 1996 and now it is widely used as the OCB in SoC designs. The AMBA protocols are the de-facto standard for 32-bit embedded processors. In 2010, ARM introduced AMBA 4. In particular, AXI4 is very suitable for the memory controller design.The DDRn SDRAM controller in this paper can receive commands from the AXI bus, and converts them into DDRn memory command sequences. We detailed from the system architecture and design specifications to the bottom of the block level design. Assertion-based design and low-power design are also discussed. In addition, we built a multi-level verification environment. This includes the interface models and the associated BFMs, controlled random stimulus, coverage metrics, protocol checker, timing simulation and STA. The DDRn SDRAM controller may be used in ARM-based SoC designs, to meet the system requirements for the higher memory bandwidth.