Thermal-Aware Power Dissipation And Delay Of Nanometer Scale Interconnect Line

The interconnect line becomes ultimate obstacle of the IC (Integrated Circuit) stepping into the nanometer scale. The propagation delay of signal along interconnect is at the same level with logic gate in nanometer scale; The dynamic power of interconnect under nanometer scale becomes significant large; The power density of IC become larger and larger when the size of die become smaller and smaller, and the inner temperature distribution becomes uniform. It is necessary to reconsider the delay and power consumption under uniform temperature distribution.Based on the RLCÏ€equivalent circuit, this Dissertation proposed a novel accurate model to evaluate Joule heat power of interconnected line in VLSI. The induction's shielding effect and the ramp-step stimulation are considered in the proposed model. The power consumption of typical interconnected topologies in 90nm CMOS process was computed. The illustration indicates the error between this method proposed and Hspice simulation is within 3%, when the input signal's delay time is less than 1ns. The proposed model are useful in estimating the interconnect power and the thermal analysis of large scale interconnect network.This dissertation focus on the delay and power dissipation of the interconnects in nanometer scale IC, and get the correlation between temperature and power consumption. This paper proposal an accurate model to estimate the energy dissipation of interconnects, and get the energy consumption of various topology structures under typical nanometer scale processing, and two kinds of interconnect topology was verified by this model. In the last chapter, the delay and the energy consumption were modeled and re-computed.and the result show that the in the same condition, the power density of interconnect did not reduce when the feature size scale down, and the error between Hspice and this model was in 15%.