Through Silicon Via Based Three Dimensional Integrated Circuits Design And Analysis

The unprecedented development of computer and information technology isdemanding Very-Large-Scale-Integration (VLSI) circuits with increasing functionalityand performance at minimum cost and power consumption. The feature size oftransistor is being aggressively shrunk to meet this demand. However, in turn, this hasintroduced some very serious problems. Interconnect propagation delay and crosstalkdistortions replace the gate delay and come to be the dominant factor limiting overallperformance and power dissipation. Additionally, with the enhancement of the chipfunctionality, the number of integrated transistors is dramatically increased, the chipsize and power dissipation continually rise and has gradually approachedtwo-dimensional (2-D) device technology limit. The production and fabrication of thetraditional plane semiconductor process encounter the insurmountable technicalbottleneck. Three dimensional (3-D) or vertical integration is emerging as a promisingsolution that can form highly integration system by vertically stacking and providecommunication among device or functional blocks within an IC with inter-planethrough silicon via (TSV), thereby providing reduced chip size, high device integrationdensity, enhanced interconnectivity, high bandwidth and low power. This thesis embarkson the a stochastic wire length distribution model, establishes a global interconnectdesign window for gig scale3-D system on chip (GSoC) by evaluating the designconstraints of global signal network; Based on3-D TSV model, it analyzes the impactof TSV electro-thermal effect on3-D interconnect propagation delay, power density andactive-layers temperature distribution; To coop with the physical limitation of traditionCopper (Cu) interconnect, it investigates the feasibility of using Carbon Nanotubes(CNTs) for interconnects application in3-D ICs. The main studies and contribution ofthis dissertation are as follows.1. Based on a stochastic wire length distributed model, the interconnect distributionof3D ICs is predicted exactly. Using the results of this model, a global interconnectdesign window for gig scale SoC is established by evaluating the constraints of wiringresource, wiring bandwidth and wiring noise. In comparison to a2D IC, the designwindow expands for a3D IC to improve the design reliability and system performance,further supporting3D ICs application in future integrated circuits design.2. After analysis of the impact of TSV parasitic resistance-capacitance (RC)parameters on interconnect performance and circuit power dissipation, closed-formdelay and power consumption expressions for buffered interconnect used in3D IC are presented. Comparative results with3D net without TSV in various cases show thatTSV RC effect has huge impact on delay and power of3D ICs that leading to extraoverhead of on average10%for maximum delay and21%for power consumption.Therefore, it is crucial to correctly establish a TSV-aware3D interconnect model in3DICs front-end design.3. Analyzing the impact of TSV size and placement on the interconnect timingperformance and signal integrity, an approach for TSV insertion in3D ICs to minimizethe propagation delay with consideration to signal reflection is presented. Simulationresults demonstrate that our approach in generally can result in a49.96%improvementin average delay, a62.28%decrease in the reflection coefficient, and the optimizationfor delay can be more effective for higher non-uniform inter-plane interconnects. Theproposed approach can be integrated into the TSV-aware design and optimization toolsfor3-D circuits to enhance system performance.4. Based a one-dimensional (1-D) heat transfer equation, an analytical heat transfermodel for3D ICs incorporating TSV effect is developed. The impact of TSV insertion,heat sink thermal resistance, thermal conductivity of back of end line and substratethickness on the thermal performance of stacked3D ICs are analyzed, Simulationresults demonstrate heat sink thermal resistance improvement is a significant way tocope with the challenge in3D-ICs thermal management. The proposed heat transfermodel can be integrated into3D ICs early-stage design and layout tools to fully takeadvantage of the electrical benefits without significant exacerbation of the thermalmanagement challenge.5. Compact equivalent circuit models for Single-Walled Carbon Nanotubes(SWCNTs) are described, and the performance of SWCNT interconnects is evaluatedand compared with traditional Cu interconnects at different interconnect levels (local,intermediate, and global) for TSV based3-D ICs. It is shown that at local level, CNTbundle interconnects exhibit lower signal delay and smaller optimal wire size. Atintermediate and global levels, delay improvement becomes more significant withtechnology scaling and increasing wire lengths. For1mm intermediate and10mm globallevel interconnects, the delay of SWCNT bundles can reach45.49%and51.84%of thatof Cu wires, respectively.