Study On High-speed IP Core For AES Algorithm

AES stands for Advanced Encryption Standards and is published by NIST (National Institute of Standards and Technology). The AES algorithm is a symmetric-key block cipher which is to replace the old Data Encryption Standard (DES). The AES algorithm can be applied into many aspects such as memory, protocol of IPSec, and WLAN technology etc. The AES algorithm can be implemented by software and hardware. With the decreasing cost of IC design, hardware implementations provide more physical security, higher speed and low cost.This paper presents a new method for the hardware implementation of the AES algorithm. Different from other methods which have only the encryption part or decryption part in hardware implementation, this paper integrates the encryption and the decryption part in the process of hardware implementation. Firstly, the decryption process is modified for the sake of sharing substructure and reducing the area requirements. Secondly, composite field arithmetic is employed to minimize the unbreakable delay incurred by look-up tables in the SubBytes/InvSubBytes transformation. Finally,8 pipelines are used to enhance the chip's frequency by analyzing the delay of hardware structure.The function of AES IP core is verified by pre-simulation and post-simulation and the result shows that the IP core achieves the best performance. The hardware structure of the AES Algorithm provided in this paper can be applied to the requirements of small chip area and high deposing date rate.