Testbench Of H.264/AVC Hardware Decoder

H.264/AVC is the video codec for next-generation multimedia, with the advantages of high coding efficiency, high transmission reliability and flexibility for operation over a variety of network environments. It has achieved a significant improment in coding efficiency, but its complexity and computation are too high. So it is usually designed as hardware accelerator in practice to do real-time encoding && decoding. To develop a high performance H.264/AVC codec chip, a powerful testbench is a must. In this thesis, based on the design && validation work of a H.264/AVC hardware decoder, a testbench of H.264/AVC hardware decoder is researched and designed in two layers:the RTL layer IP simulation environment and the system prototype validation environment.In the RTL layer IP simulation environment, the function design and logic correctness of the H.264/AVC hardware decoder are verified. The directory architecture of test case is designed according to the H.264/AVC stream structure, and an automatic test case generation tool is developed based on the JM reference software. Test case includes two parts:the stimulation and the reference result. The stimulation part is used to enable hardware decoder to work, and the reference result part can be used as reference data to be compared with the decoding result of hardware decoder. The data that will be compared includes not only the final YUV picture data, but also the data out from each module. By this comparison, it can be easily found which module has the bug.In the system prototype validation environment, it is verified that whether the hardware decoder can work normally in the SoC environment. The environment includes two parts: hardware and software. Hardware part is the Artemis audio/video SoC platform. Software part is a complete audio/video decoding system, including audio/vedio stream abstraction, audio/video decoding, video post process, and so on. Audio can be played through IIS interface; video can be shown by LCD screen.The baseline profile of the H.264/AVC hardware decoder has been totally verified and can work very well on the FPGA board.