Research On Key Techniques Of High Speed Clock And Data Recovery Circuits For 60GHz QPSK Receiver

With the rapid development of information technology,the data processing ability of electronic products is increasingly higher,so as the demand for the speed of wire and wireless transmission.Due to the resource strain of traditional spectrum wireless transmission and its failure to keep up with the speed need,60-GHz wireless high frequency transmission becomes the most popular high-speed communication method.As a critical module in 60-GHz receiver,the Clock and Data Recovery(CDR)is responsible for adjusting the sampling clock's phase to the data,eliminating the data amplitude distortion and jitter,and recovering the high-quality data at a low bit error rate.This thesis presents a half-rate CDR which is based on the Tsmc 65 nm CMOS technology and applied to the 60 GHz wireless transceiver.First,the Phase Interpolator(PI)structure is adopted after the analysis and comparison among commonly used CDR structures.And comprehensively considering the needs of receiving system and the loop reliability,a half-rate CDR structure based on PI is confirmed.Next,an introduction to the 60-GHz wireless receiver structure and the CDR's function is given.With a linear analysis on Bang-Bang Phase Detector(BBPD),the system model is built and verified.Then,a detailed introduction is made for every module,including its structure and parameters.At last,a description of the simulation environment and the key points in the layout design is made.And the post-layout simulation result of main modules and the whole loop is given out and analyzed based on the theory.A relatively complete simulation method is designed in this thesis to estimate the system performance.The design parameters here are based on the need of the 60-GHz wireless receiver,in which analog circuits are replaced by digital circuits as much as possible and half-rate PD and double edge-triggered sampler are used.This has reduced the circuit area and power consumption.Furthermore,the application of DC Offset Cancellation(DCOC)circuit has improved the system stability,and the utilization of Duty Cycle Corrector(DCC)has adjusted the clock duty to 50%,guaranteeing the accuracy of the double edge-triggered sampler.With the supply voltage of 1.0V,I branch of the half-rate CDR operates from 1.25 Gbps to 6.4Gbps,and the total data rate is between 2.5Gbps and 12.8Gbps in the consumption of 17.44 mW.In this condition,the maximum clock frequency offset tolerance is 100 ppm.