The Analysis On Stress And Preformance Of Nanoscale MOSFET

As the feature size of CMOS device entered the nanoscale, the traditional materialswill approach their physical limits and technology limits. Therefore, to explore newdevice materials and new device structure has become an important choice to improvethe performance of integrated circuit. Strained Si is a new technology which emerges inthis environment. It can effectively increase the carrier mobility, thereby improve deviceperformance. Stress is the key factor which can increase the mobility. In this paper theresearch focuses on the stress and electrical properties of strained Si device channel.Firstly, this article uses the finite element simulation software ANSYS to analyze thechannel stress of the PMOS with SiGe S/D and the NMOS with SiC S/D, and makes adetailed research on the factors which influence the channel stress distribution. Theresearch shows that the channel stress distribution of strained silicon device can becontrolled by adjusting the structure parameters, meanwhile, it is found that the NMOSand PMOS channel stress can be controlled by the material content the length ofchannel and the junction depth of S/D. Secondly, the research on the stress distributionand electrical properties of the PMOS with SiGe S/D and the NMOS with the SiNcapping layer is done by using Sentaurus in this paper. The stress distribution obtainedby Sentaurus is in accord with the stress distribution obtained by ANSYS. The researchof electrical properties illustrates that high tensile stress SiN cap layer and SiGe S/Dstructure can be used to enhance electrical properties of NMOS and PMOS respectively.For example, applying1Gpa stress to a NMOSFET with the SiN capping layer, thesaturation current of it rises26.8%, and the Gm of it rises28.6%. Finally, according tothe mobility enhancement mechanism of the strain device, the stress property of strainedSi channel is analyzed.Through the research on the stress and performance of strained Si, this paperprovides the foundation for the experiments analysis, and the base for devicemanufacture.