Research On Strained Silicon Nano MOS Device

After entering the nano era, with the device size decreases, the performance ofMOS devices is greatly affected by many physical and technological limitations byscaled down. The strained silicon technology, which has the high carrier mobility andconventional silicon technology, become one of the technologies which make thedevelopment of integrated circuits keep on the rate of Moore’s Law.This paper discusses the basic physical properties of strained silicon，such aslattice structure，carrier mobility and band structure. This paper also elaborates theintroduction method of nano-scale N/P MOS device of strained silicon stress in order tolay the theoretical and technical foundation for future research work.Based on the various problems of nano-MOS devices, the paper focuses on thestructure of source/drain and channel. Source/drain aquire SDE structure to suppresshot-carrier effects. Channel using Halo structure and reverse-doping structure to avoidthe punch-through effect.This paper research and optimize the device structure for the65nmNMOSstrained silicon devices. Firstly analysis the impact of the thickness of SiN film, theintrinsic stress on SiN film and the thickness of the poly silicon gate on the introductionof channel stress. Secondly, the paper not only optimize the parameters that affect stressand stress distribution, but also simulate the structure proposed by nano devices. Finallythe optimized structure parameters of the65nmNMOS strained silicon devices isobtained.