A Novel TSV Structure And Numerical Simulation Of Thermos-Stress For 3D Package

In recent years,Through Silicon Via(TSV)technology becomes the mainstream of 3D packaging-process,which realizes the interconnection by creating TSVs between the chips or wafers.However,the 3D TSV packaging technology leads to a sharp increase in power density of the chip,which causes serious heat dissipation problem.And the thermal stress caused by temperature increase and the mismatch of coefficient of thermal expansion between varieties of materials is also more prominent.Severe thermal stress mismatch will cause the interconnect failure of the TSV package.Therefore,the research on TSV thermal problem and thermal stress is the key to the development of this technology.Firstly,a model of 3D TSV package was established to analyze the temperature and thermal stress distribution.The effect of TSV height,diameter and pitch on thermal performance and thermal stress was analyzed by using orthogonal test.A novel TSV structure was then proposed to solve the problems existed in TSV technology,such as thermal dispersion,thermodynamic mismatch,and etc.A layer of carbon materials was added in the novel TSV structure due to its excellent thermal and mechanical characteristics.The finite element analysis method was used to study the performance of the proposed TSV structure on heat conduction and release of thermal stress,which was expected to solve the problems of TSV process in new technology node.Finally,the fabrication of the novel TSV structure was tried,which includes etching of silicon vias,deposition of functional layers,the growth method of carbon nanomaterials and filling of the vias.The results provide new ideas for the design,manufacturing and performance analysis of TSV structure in 3D packaging technology.