Simulation And Analysis Of Thermal Stress Of Cu Interconnect Structure In IC

With the IC development to the era of deep submicron technology, Cu/Low-k interconnect has replaced Al/SiO2interconnect. Cu interconnect is an important factor to determine the IC performance, reliability, productivity and cost. However, the reliability of Cu interconnect has a direct impact on chip integration, device density, clock frequency and power, and it has become the main issue of people to care, especially the reliability of the stress transfer has become serious challenges in the copper processing.In this paper, build up a three-dimensional (3D) finite element model to analyzes the thermal stress distribution of Cu interconnect system with ANSYS finite element analysis software. And on this basis to explain the characteristics of thermal stress influence with the different structure and different materials of Cu interconnect. First of all, change the barrier materials for Cu interconnect lines and the barrier layer thickness to get the comparative analysis of the influence of Cu interconnect barrier layer materials for thermal stress. Second, analyzes the influence of different dielectric materials of copper interconnection for the thermal stress. Finally, study the thermal stress of Cu interconnect with novel Cu interconnects structure. Through the study of this paper, the results provide a reference for the improvement of the stress migration, and are used to guide circuit layout.The simulation results show that the thermal stress increases with the diffusion barrier thickness increasing, and compared with TaN, ZrN as the copper interconnect barrier layer materials is more superior, the thermal stress of Cu interconnect structure is reduced. Using the low-k dielectric material based high polymer instead of the traditional SiOx, the tensile stress of Cu interconnect is decreased obviously. Through the analysis of the performance parameters of the dielectric substance materials, explain it is effective to relieve the structure of Cu interconnect plastic deformation that by reducing CTE(Cofficient of Thermal Expansion) of low-k material or improving low-k materials young’s modulus in some limits inside. Through comparing the failure modes of the Cu/TEOS structure and Cu/SiLK structure, learn that the thermal stress at Cu/via interface is reduced with via gouging depth increase. So the possibility that there are cavities or the cavities nucleation in the via bottom interface is smaller, and Cu interconnect system deformation is also smaller. Via with dielectric slot suffered lower hydrostatic stress at the Cu cap/via interface than the via without dielectric slot.