Timing Analysis And Post-Simulation For FPGA Based On LUT

A timing analysis method and a post simulation design FPGA based on LUT are proposed and implemented in this thesis. Timing analysis and Post-Simulation are operated after placement and routing, which are two indispensable steps of the FPGA supporting software. In the stage of timing analysis, timing node and timing edge, which are extracted from chip architecture and routing data, are used for building the timing graph. According to the timing graph, the delay values and critical paths of circuits are computed. Through calling methods of graphic interface, the delay values are printed and paths between inputs and outputs are highlighted. The problem of lacking in detail delay values of circuit is solved and then the necessary information for simulation after placement and routing are provided. In the stage of Post-Simulation, a tool called Post-Simulator is designed. According to the input signal, the Post-Simulator traverses timing graph and addresses LUT memory, the output signal of circuit can be obtained, and then combining of the delay data of timing analysis, post simulation wave file can be generated. Waveform will be displayed in the Waveform Analyzer. Post-Simulation further verifies timing and logic functions of circuits.