Design And Implementation Of ADM In SDH

Backbone network of telecommunicate is composed of SDH elements in the mass of worldwide countries, so do china. SDH elements is rather rigor, SDH has complicated recommendations and configuration. Because of causations above, ASIC is the trend of evolution, core circuits of SDH elements are implemented by ASIC. Add/Drop Multiplexer is allocated for switching stations, ADM has widely application in SDH network. It assembles Synchronization-Multiplexing and Digital Cross-Connects, it can add and drop arbitrary tributary signals therefore it is rather flexible. Core chips of ADM rely on import, so it's exigent for us to design and research such chips.This paper firstly describes knowledge related to ADM, including SDH information and interrelated technology. Macro design project of ADM is presented in succession. The multiplexing path is 2Mbit/s tol55Mbit/s, in order to upload and download E1 signals from STM-1 ADM. The ADM has three chief parts: E1/ STM-1 Multiplexing System, STM-1/E1 De-Multiplexing System and Digital Cross-Connects System. The former two even more importmant and hardcore. This paper provides detailed design project of the former two, it focus on the design and implementation of E1/ STM-1 Multiplexer and STM-1/E1 De-Multiplexer.Top-Down design methodology is adopted through this paper, RTL-lever Verilog HDL source codes are compiled independently. The software environment are Xilinx University Program ISE 9.1i edition and VCS of Synopsys, Inc. The first process of design flow is Behavioral Simulation by VCS. Secondly the environment is converted to ISE, Spartan-3E Series XC3S500E-4FG320C is configured as FPGA device, and accomplishs Synthesis by Synplify Pro 8.1. Then do Translate, Map, Place&route ordinally, which are three processes of Implementation. Fourthly Post Simulation is divided into three processes: Post-Translate Simulation, Post-Map Simulation, Post-Route Simulation. Finally, load correlative files into FPGA board and verify the device. Verified result substantiates the feasibility of the design.According to ITU-T Recommendations and national standards, the source codes of E1/VC-4 Multiplexing System and STM-1/TU-12 De-Multiplexing System are finished independently. Finally the design passed FPGA validation, the leading methods of that are Behavioral Simulation and Post Simulation.