Radiation Effects And Hardening Techniques Of Deep Submicron And Nano-scale Integrated Circuits

With the continuous progresses of aerospace technology and intensive scientific researches on nuclear physics in our country,there are increasing demands for the radiation hardened integrated circuits.On the one hand,the development of radiation hardened chips is still in its infancy domestically.On the other hand,the high performance radiation hardened chips have been the primary targets of technology blockade and product embargo in western developed countries.The radiation hardened chips in our key technical areas,which have been long subject to technology leading countries,have not yet been completely autonomous.Therefore,the research on radiation effects of integrated circuits and radiation hardening techniques will greatly promote the development of national defense and modernization.The technology of IC design is transitioning from deep submicron to nanometer level,meanwhile,the radiation effects and radiation hardening techniques have changed rapidly.At the 0.18 ?m technology node and above,the total ionizing dose(TID)effect is relatively significant since the gate oxide and field oxide are both quite thick.With the technology node scaling under 65 nm,the TID effect is greatly reduced thanks to the thinning of gate oxide and the emergence of shallow trench isolation(STI)technology,which make the TID effect no longer the main radiation damage factor.However,with technology scaling,the soft errors induced by single event effects(SEE)are increasingly serious to ICs,which have even outweighed the sum of all the other failure factors and become the primary issue of circuit reliability.In this work,the research on the radiation effects and radiation hardening techniques of 0.18 ?m and 65 nm bulk CMOS transistors and circuits is conducted with the research findings as follows,(1)The TID irradiation experiments were carried out on the 0.18 ?m bulk CMOS core and I/O NMOSFETs,and the variations of the transistors' electrical characteristics were obtained.The research results show that the electrical characteristics of irradiated transistors degrade with the sub-threshold drain current increases and the threshold voltage shifts with increasing TID level.The TID effect of I/O transistor is more severe than core transistor,and the TID effect of narrow channel transistor is more severe than wide channel transistor due to the radiation induced narrow channel effect(RINCE).The negative body bias helps mitigating TID effect of transistors at the cost of lower driving capabilities at the saturation region.The SPICE models with TID effect included for 0.18 ?m bulk CMOS strip-type and edgeless NMOSFETs were derived by the transistor irradiation experiments and device parameter extractions.The simulation results with the SPICE models comply well with the irradiation results,proving the capabilities of the SPICE models in predicting the TID responses of transistors and circuits.(2)The generation and propagation of SET pulses in the combinational logic digital circuits are studied.The research results show that the SET current peak and the duration time increase with increasing LET value of the incident heavy ion.The SET current shape turns out to be a narrow spike followed by a long plateau period which is significantly different with the double exponential pattern usually observed in the isolated single transistor without electrical coupling with other transistors in the circuit.As a result,the mixed mode simulations with both the TCAD and the SPICE models provide better predictions of the SEE in the circuits.The wide channel transistor incurs shorter SET pulses than the narrow channel transistor,and so does the short channel transistor compared with the long channel transistor.In actual design,short and wide transistors are preferred for the sake of SET mitigation.(3)The physical mechanisms of SEU in the temporal logic digital circuits are studied.The research results show that the SEU cross section of the 0.18 ?m unhardened standard 6T SRAM is higher than that of 65 nm SRAM which can be attributed to the reduction of sensitive volume and hence charge collection amount at scaled technology node.(4)The influences of the technology scaling,higher operating frequency,etc.,on the SEE of circuits are studied.The research results show that more well contacts and smaller spaces between contacts and transistors help to reduce the SET pulse width and alleviate the well potential modulation,thus mitigate the SEE.In the large angle incidences,the charge sharing between adjacent transistors is enhanced,hence the SET pulse width can be decreased by the pulse quenching effect.The deep N-well process can effectively cut off the funneling length induced by the ion incidence,thus reduce the charge collection amount at the sensitive node and incur shorter SET pulses compared with ordinary twin-well process.(5)A novel SEU hardened SRAM bit-cell design is proposed.The critical charge of the proposed cell is up to 12,320 f C,which is more than 1,000 times higher than that of the unhardened 6T SRAM cell and significantly higher than other hardened designs at low area and electrical costs,promising high performance and high reliability in harsh radiation environment applications.(6)A radiation hardened standard digital cell library is developed with the 65 nm bulk CMOS process,which can be used in the design of radiation hardened chips.(7)Two radiation hardened chips are developed by the 0.18 ?m and 65 nm bulk CMOS processes,respectively.The forward body bias method for characterizing TID effect in the CMOS integrated circuits is proposed,which is validated by comparison with the simulation results of the transistor SPICE models with TID effect included.A high speed data multiplexer circuit is proposed which avoids the possibility of data penetration in the conventional multiplexers.An extra benefit of this circuit is the natural synchronization characteristics in cascade use.A band calibration algorithm for wide band PLL VCO is designed.Two VCOs covering ultra-high frequency range can be calibrated within short period with high precision.