Research And Design On Crosstalk Avoidance Coding For Low Power Buses

Crosstalk induced delay, power consumption, and noise in deep submicron on-chip buses are the main facts restricting the performance and reliability of the buses. Through low power coding, crosstalk avoidance coding, and error detecting (or correcting) coding, these issues can be solved effectively. Consequently, the performance and reliability of buses are improved considerably while dynamic power consumed in buses is reduced.Based on the recent trend of the bus coding researches both at home and abroad, the general concepts and researching methods of bus coding are summarized. By employing deep submicron bus model and the unified bus coding framework, a low power adaptive spatio-temporal bus coding scheme for crosstalk avoidance is proposed to reduce crosstalk induced delay and power consumption in deep submicron buses. The proposed scheme is evaluated using the SPEC benchmarks. The results show that the proposed scheme improves the throughput by 62.59% to 81.62% over the un-coded approach and reduces the power consumption by 14.63% to 54.67% compared to the other similar schemes while eliminating the worst case crosstalk with only 7 wires overhead for a 32 bit bus. The scheme achieves a good enhancement in dynamic power, wiring overhead, and performance. Furthermore, the proposed scheme is mapped into a reusable hard macro block by using IP design technology. A layout-accurate analysis is performed for the critical character, timing, area, and power of the macro. Meanwhile, a whole verification environment, including encoder and decoder, was established for evaluating the flexibility and effectiveness of the proposed scheme from a physical implementation level. Preliminary studies were completed on the physical implementation, verification, and application of bus coding schemes.