Physical Design Study Of YAK SOC Chip

When the development of VLSI technology step into deep-submicron level (DSM), the impact of interconnect effect in VLSI become more important than before. Interconnect delay, Crosstalk Effect, IR-Drop, EM Effect, Process Antenna Effect have become the bottle-neck of the physical design and brings new challenge.Five interconnect effect mentioned above are analyzed detailed in this paper. Method to prevent and fix interconnect effect is used in YAK SOC chip's design, ensuring the continuous convergence and manufacturability under timing driven.Logic synthesis, physical design and verification of YAK SOC are presented in this paper. Some important process such as floorplanning, IO placement, clock synthesis, routing are analyzed. The physical design of YAK SOC is completed successful. The GDSII layout file could fulfill with the timing requirement and implement the anticipative function. Since DRC and LVS verification process have finished, this layout is able to tape out.YAK SOC is a SOC chip designed by our lab. Its area is 3200μm?3300μm. It use HJTC's 180nm technology and is operated at 50 MHz. The chip is used in Bluetooth or RFID.The research result of this paper has some directive meaning and applicable value in physical design and optimization for VLSI under deep-submicron technology.