The Analysis And Realization Of Routing Algorithm For Crosstalk Reduction Under Deep Submicron Technology

With the development of very large scale integrated circuit(VLSI) entering into the stage of deep submicron technology, higher speed and lower power have been the main feature of the current integrated circuit. We are confronted with new challenge in order to design such high-powered chips. That is, chips run with higher speed while their size reduce and the system is more complicated but can still work stably. In this case, some secondary negative effect in the lower speed system design becomes notably such as signal integrity.The space between wires has been reduced and the same as the relative space because of the increased wire thickness. The coupled capacitance of two adjacent wires even exceeds the ground capacitance. One of the effect of coupled capacitance is crosstalk noise, it may arose logic errors. Another effect is crosstalk delay, it may accelerate or slower the signal propagation so as to cause setup time violation or hold time violation. So a lot of people are researching various algorithm to solve the above problem.In this paper, we analyze models of crosstalk delay calculation and crosstalk noise calculation firstly. Then, we analyze typical optimal algorithm based on both Non-Manhattan and Manhattan channel routing. According to the above analysis, we give a non-grid optimal algorithm to reduce the crosstalk effect which is based on splitting horizontal line into sub-lines. We analyze the model of this algorithm,the process of how to realize it,the time complexity and space complexity. We can get good result in addition to more quickly running time than another algorithm. At last, we test the algorithm with two different methods. One is traditional method in the reference paper described as follows: input the sample layout and compare the initial crosstalk with crosstalk after optimization. Another method is as follows: we analyze crosstalk delay slack and crosstalk noise slack reported by backend timing analysis tool to see the improvement after applying the algorithm.