A Study Of Deep-Submicron Interconnect Effect And Physical Design Of H.264/AVC-AVS Video Decoder Chip

Along with the development of VLSI technology coming into deep-submicron level (DSM), interconnect parasitic effects of metal wire could have severe impact on the physical design of VLSI. For example, IR Voltage Drop Effect, EM Effect, Crosstalk Effect and Process Antenna Effect (PAE) have become the bottle-neck of the physical design under deep-submicron process. These four potential failures, caused by interconnect effect, affect chip reliability badly.According to the requirement of physical design and optimization, and consider-ing the possible underlying problems due to deep submicron interconnect effects, the inducing mechanisms, the imperilment of the four failures mentioned above are ana-lyzed detailedly in this paper. Based on the Cadence SoC Encounter Digital IC Design Platform, new ways of violation preventing and fixing, physical design and built-in iteration flow are discussed designedly in this paper. Furthermore, aiming at the criti-cal requirement both of area and timing in complex chip design, an optimized PAE preventing and fixing iteration flow is proposed in this paper, which improves PAE prevention/fixing efficiency, reduces chip area and the iterating times, on the precon-dition of achieving good performance and timing convergence.The above methods have been effectively adopted in the back-end design of the "Phoenix II" H.264/AVC-AVS video decoder chip, ensuring a success in chip manu-facturing strongly.The research result of this paper not only has application value but also some useful innovative meaning in the modern deep submicron VLSI physical design.