Research On The Design Of Test Structure For Three Dimensional SoC And Its Optimization

With the advancement of the scale of Integrated Circuits (IC), thecharacteristic size of ICs is decreasing continueously. Whereas, the interconnectwire length, especially the global interconnect wire length does not decrease in thesame proportion. Hence, conventional2D ICs seem to be much more crowded, andthe delay on the wire is becoming a larger part of the whole delay, with powerdissipation growing dramatically. These factors are bottleneck in the developmentof IC. Under this background, three-dimentional (3D) IC comes into being.3DSystem-on-Chip (SoC) testing acts as a significant measure to guarantee thestability of3D SoC when it is going from just a concept to application.This dissertation introduces the approach of3D SoC test architecture design.Firstly, makes a comparision on2D and3D SoC test architecture. Based oninternational standard, the dissertation shows detail test structure and test accessmachenis m (TAM) design method. On top of that, makes a simulation of two caseswhen testing circuits in serial and in parallel. What is more, test architecture designis the basement of test architecture optimization, with3D SoC test-wrapperoptimization and3D SoC test scheduling being included.Test-wrapper optimization is recognized as an effective solution for saving testtime of embedded cores.3D integration, which is beneficial for integrated design,brings test-wrapper optimization new challenge. In this dissertation, considering thecase of the medium-granularity partitioning, a test-wrapper optimized approachbased on Referenced Length (RL) guidance and layer hypothesis is proposedaiming at balancing the length of wrapper chains so as to shorten the scan test timeof3D case. During the optimization, RL is used to restrict the longest wrapperchain length. Layer hypothesis is put forward and used between RL-guidedelements placing process and RL-adjusting. The TSV number is calculated.Experiments results show that the proposed approach is effective and the TSVnumber is really small.Taking the case that varied granularity IP cores are inc luded in a3D SoC intoconsideration, a test scheduling algorithm is proposed to save the test time of thewhole3D chip. According to SoC’s scale and floor plan, the mathematic model oftest scheduling is introduced and solved to determine the test order of each IP core under power or temperature constraints. Test scheduling algorithms based on3DSoC consists of hard-and soft-cores under power and temperature constraints arealso put forward. ILP tool is utilized to solve the model. Experiments on ITC’02and ISCAS’89benchmarks show that the approach reduces the test time of3D SoCeffectively under constraints. The results are also utilized as guidance for thedesigners to decide which kind of or what scale of IP cores to use, and to determinehow to place varied core rescources in order to benefit the integrated and test periodof a3D SoC.