The Research On Readout Circuit Of CMOS Image Sensor Based On Bipolar Photogate Transistor

In this paper, the developing history, present situation and trends of CMOS image sensor inside and outside of China were summarized. The characteristics between CMOS image sensor and CCD image sensor were compared and the research meaning was pointed out. On the basis of introducing semiconductor photoelectric effect, the light-transfer characteristics of photodiode and photogate transistor used in CMOS image sensor were deeply discussed, the factors affecting the light-transfer characteristics of photodiode and the methods increasing the light-transfer characteristics of photodiode were analyzed. The equivalent circuit model of new photoconducting device—bipolar junction photogate transistor (BJPHGT) was proposed, by utilizing electronic circuit simulation software PSPICE, the current-illumination characteristics of BJPHGT were simulated. Due to the introduced P+N injection junction, the photoresponse characteristic of BJPHGT is better than that of traditional photogate transistor. The photocurrent density increases exponentially with the incident light power. After every kind of pixel unit circuit was introduced, the new pixel unit circuit for BJPHGT was brought forward and its noisiness was analyzed. By means of adding two transistors in each column bus, making them form a short-circuit differential amplifier with source follower transistor and row switch transistor inside of pixel, the photoelectric conversion gain is increased by this method. In the correlated double sample circuit, by substituting unity gain sampler for PMOS column gate, not only the nonideal effect of switch transistor was depressed but also the photoelectric conversion gain was further increased. A column output buffer used to drive large input capacity of analog-digital converter (ADC) and a column parallel, 8-bits resolution, low consumed power successive approximation type ADC for CMOS image sensor were designed. Its sample speed, signal-to-noise ratio, differential and integration nonlinear are 1MS/s, 42dB, 0.5LSB and 1LSB respectively. The comparator was designed to be a fully differential multilevel structure, the first and second level are pre-magnification, and the third one is amplifiers. The charge-scaling digital-analog converter has a new capacity distribution, which make its specific capacitance decrease greatly. The successive approximation register is made up by least logic elements. All these methods leads to very low power consumption which is 350μW.This design have a perfect compromise of power consumption, noise, area and speed and is propitious to reduce the power consumption of CMOS image sensor system, avoid producing hot spot due to high power consumption of the local circuit which damages the performance of CMOS image sensor.