The Study And Design Of Radar Clutter Processor For VTS

In the VTS (Vessel Traffic Services), the capability of processing radar clutter has become a main factor which limits the capability and reliability of target-extracting and target-tracking of radar. With the construction of regional VTS, it is required that the radar signal should be transmitted with the highest quality and lowest cost, and the key technology to meet the requirement, which lies in the compression of radar information, is affected due to the existence of radar clutter. For the above reasons, a study on more efficient technology of processing of radar clutter in VTS is very valuable and practicable.This dissertation is based on the works of former researchers. We are concerned with the principles, approaches, performance properties, studied and designed radar clutter processor.On the basis of the above theoretical analysis, we have studied and worked out the scheme of the radar clutter CFAR processor based on statistics characteristic and the radar clutter CFAR processor based on wavelet transform. By contrasting the result of Matlab simulating and experimenting of three different distributing of simulating radar clutter and real radar clutter data, we get that CFAR processing is very available for the factors. The main target of this paper is to study radar clutter CFAR with wavelet transform technology ,and carry out it with FPGA(Field Programmable Gate Array).The result of simulating experiments and practice shows that the radar clutter CFAR processor in this paper have very good suppression on the echo of sea, rain, snow and land. The processor can effectively suppress the pinnacle composition of the radar clutter without the loss of decreasing the resolution of target, and significantly improve the SNR.