Research Of DBF And Signal Processing Technology Of Shipborne3D Radar Based On FPGA

With the development of radar signal processing technology, radar systems have put forward higher requirements on the performance of digital signal processor, including the need for more on-chip resources and faster processing speed, etc. Field-programmable gate array (FPGA) has a parallel processing architecture, configurable IO pins and ample hard-core DSP resources, which can complete the task of radar signal processing better. Therefore, FPGA is gradually becoming the core device of radar signal processing system.Parallel bus technology, such as PCI and VME, are widely used in the radar signal processing system. With the rising demand for radar signal and data processing speed, bus bandwidth and working environment by radar tasks, the radar signal processing system based on the traditional parallel bus can hardly meet the requirements of actual research and development. The signal processing platform based on VPX serial bus standard has powerful signal processing capabilities, I/O capacity and high-performance network switching capability, so VPX bus will give full play to its advantages. More and more radar systems will use VPX bus standard in the future.This paper is based on the one-dimensional DBF radar project. It designs the architecture of the radar signal processing subsystem. The whole system based on the newest VPX high-speed serial bus and combined with high-performance FPGA processors for powerful signal processing capabilities sets up a high performance parallel computing platform for radar system. The system requires more signal processing tasks are completed in the FPGA, thus the system device volume, size and weight can be greatly improved.In this paper, the signal processing in the system is described in detail, and has been carried on the Matlab simulation, including pulse signal generation, DDC, pulse compression, moving target processing, CFAR detection and digital beam forming, etc; algorithm validation of the collected echo data based on Matlab is completed; DBF beam forming and a series of signal processing functions are implemented in FPGA; for anti-frequency interference, joined the anti asynchronous processing; in order to restrain the low-speed clutter effectively, a realization method of clutter’s velocity map based on FPGA is studied. Finally, the signal processing subsystem designed in this paper has been well applied in practical radar systems.