Study On Power Estimation Methodology & Correlative Problem In VDSM Integrated Circuit

As the rapid development of the IC technology, IC industry has entered the deep-sub micro and nanoscale era. However, the huge gap between technology and design capability brought new challenge to the design methodology. In the past, the VLSI designer's concerns concentrated mainly on tradeoff between chip size and speed. Recently, the tremendous demands of the modern communication and consumer product market, especially which of the portable and wireless products require IC to feature lower power, smaller volume as well as higher performances. Thus the power as well as the size and speed has become the VLSI designer's focus. The low power design is concerned in two problems, power analysis and power optimization. Between them, the power analysis is mainly concerned about the accurate estimation of the power dissipation to ensure that the power specifications are always satisfied during different phases of the design process and results in success in the design.Due to its importance, a lot of efforts have been put into the research on average power estimation methodologies and EDA tools. The research of this dissertation focuses on the leakage power estimation, maximum power estimation in different logic circuits and the application of gated clock cell in low power design.Firstly, the power model corresponding to each component in CMOS circuits was introduced and the dynamic and static method for power estimation was summarized. Secondly, a leakage power estimation method based on GA (genetic algorithm) was proposed for CMOS circuits according to the static power dissipation depend upon the state of circuits when they worked in standby or idle mode. By it, the input vectors that produce the minimum leakage power could be searched out when circuit worked in standby or idle mode. The estimation results can help designer to modify design. When circuit worked in standby or idle mode, the minimum leakage vectors can be applied to the primary inputs or block inputs by additional circuit module to reduce the leakage power.Thirdly, since the leakage power of SRAM cannot be estimated by gate-level EDA tools due to its analogy feature, a power estimation method of SRAM based on simulation was presented in chapter 4. After analyzing the producing mechanism of leakage power for each sub-circuit in SRAM, A leakage power model for each sub-circuit was established to estimate the leakage power for full SRAM.Because the maximum power dissipation of circuit affects on the reliable and the design of power line as well as ground line, etc., a new power estimation approach based on GSAA (genetic-simulated annealing algorithm) was proposed for CMOS combinational circuit in chapter 5. The simulation result showed that compared with GA, the GSAA is more accurate and faster. In the chapter 6, GSAA was applied to CMOS sequential circuits and its validity was well verified by the simulation results.Power optimization is a complicated issue and covers a lot of knowledge areas. Gated clock technology, as a methodology to reduce power dissipation, was discussed in detail in chapter 7. In this chapter, the steps that a gated clock structure designed as a physical cell was present. This method was successfully applied to the design of a low power high performance embedded, CPU-ck510. The practice of its physical design proved that it made the analysis, verification and back end design of circuits much easy and convenient to treat a gated clock structure as an IP. The test results showed that the chip works well.