| Technology scaling has enabled the number of computing resources on a single chip. In these multi-processor System-on-Chip (MPSoC) environments, interconnection among resources is one of the challenging issues. Network-on-Chip (NoC) is the latest evaluation in SoC design where communication channel is established by using networking technology. This dissertation covers some of the key and challenging design issues specific to the NoC architecture.;This dissertation suggests Networked Processor Array (NePA) for MPSoC platform, covered by three topics: a robust adaptive router, a novel clock boosting mechanism, and a generic network interface (NI). First, an adaptive routing algorithm and architecture for an NoC is presented. The adaptive router adopts a wormhole switching technique and its routing algorithm is livelock-/deadlock-free in 2D-mesh topology. The performance and its hardware complexity of the router demonstrate the feasibility of on-chip interconnection network for an MPSoC. Second, a novel clock boosting mechanism to increase performance of an adaptive router is proposed. One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the route decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits, because the body flit can continue advancing along the reserved path. The experimental results show that the clock boosting mechanism enhances performance of the baseline router by increasing throughput and decreasing the average latency. Third, a generic network interface is proposed for the reuse of IP cores in plug-and-play. Possible IP cores are classified and an allocation table for a modular wrapper design is presented. The case studies in memory and turbo decoder cores demonstrate the feasibility and efficiency of the proposed architecture.;The ultimate goal of this dissertation is to provide power-aware on-chip interconnection network for MPSoC design. The energy and power issues in NoC are covered, starting with micro-architectural level techniques, followed by system level approaches. A novel dynamic frequency scaling (DFS) link is proposed by adopting the clock boosting mechanism and history-based DFS policy allows network power scale with changing workload. Finally, a semi-automated power estimation framework is proposed, enabling power exploration at system level. As interconnection network is currently the limiting factor for MPSoC realization, the techniques presented in this dissertation are enabling technology for a new class of real-world, high-performance computing systems. |
