Font Size: a A A

The Research Of Real-time Wireless Measuring On Speed Skating Pressure

Posted on:2006-07-24Degree:MasterType:Thesis
Country:ChinaCandidate:X D ZhangFull Text:PDF
GTID:2168360155453351Subject:Mechanical and electrical engineering
Abstract/Summary:PDF Full Text Request
1. The problem for discussion This is the project cooperated with ice-sports center of jilin province in research of the situation of athletes'force on the ice in the course of physical training. By measuring the real-time pressure on ice and with the picture of pose of athletes, we analyze athletes'move characters, for the purpose of instruction in training. The wireless transmission of the data is an important content in the measuring and detection system. In modern communication, the interference of the signals is more and more serious, there are more and more categories--interfering in industry, various of artificial disturbance and mutual interference of other radio signals, so if adopt the transmission means of the wireless data, the transmission equipment must possess stronger anti-interference ability , could fulfill the requirement that the data are transmitted reliably . In the system of wireless communication, Channel code is good and effective way in reducing error code in the transmission course, so the channel code has been the important component in the wireless communication system all the time. With the development of integrated circuit, the decipher chip using the integrated circuit of the small area but finishing the high speed , high performance , low consumption has been a focal point studied all the time. 2. Difficult point of the subject Subject need to make accurate measurement on the ice-skates strength and side direction strength, and can't change support structure of ice-skates of shoes, so the requisition for sensor is high, try one's best to avoid producing the non-linear and question coupled. We need to measure strength and side direction strength of the knife of skate-shoe rapidly in real-time in addition, the high speed operation is necessary. Because the wireless signal should be influenced by various kinds of interference during the process of transmitting, in order to guarantee accuracy, make the transmission of the data in certain code-error quotiety, must take the measure of good anti-interference, but will exert an influence on the speed of signal transmission, so on the premise of satisfied speed transmitted, improve anti-interference ability that is the question this text should discuss to. By adopting the convolution code of viterbi decipher algorithms to carry on the channel code in error-correcting system. The mistake will be made the automatic correction in the error-correcting decoder transmitted, the real-time character of the decipher is good, systematic operation speed quick. But the decode algorithm is complicated, how realize high-speed decipher algorithm of viterbi at one chip of FPGA, ACEX of 1k50, and optimize each module of viterbi decipher, realize the rational distribution of FPGA chip's area and speed of decipher, become the difficult point of this text. The systems must be tested on its ability in correcting error, it is a very important content in the whole design .To appraise error-correcting performance a large number of data of test of decipher is needed, and the code-error quotiety calculation will be difficult . 3. Overall design of the wireless measuring system This systematic function is to make real-time measurement to the size of icing strength in speed skating. The whole is composed by the design of data gather; data receive and channel code mainly. The data out from the sensor enter into the data gathering system. After the instrument amplifier is amplified, we use 2051 one-chip computers as controlling the chip, adopt A/D change chip--TLC2543 which comes from TI Company using the serial structure of inputting, changes the speed fast. One-chip computer output digital signal through transmit chip to be F05 wireless to transmit, go to location plane through receive chip RX3310 receive after the signal, input the data to the computer through one bunch of mouths. Because the influence that will be interfered in the wireless transmission course of the data, is especially interfering the serious environment, the quality of influence signal transmission that will beserious, so carry on the channel code in order to improve the transmission quality of the signal before the wireless is transmitted, adopt FPGA to decode the channel after the signal receive of the location going to machine. 4. The Design of Viterbi Decoder Viterbi decoders mainly divides into 7 pieces of module according to the function. Systematic block diagram as Fig. 1 shows, mainly by BMG it (whether route calculate module), ACS (add than select the module), MMU (whether state route is it manage module to store), TB (whether route track back module), SMU (whether route stores the module ), is it output module add another control circuit to be that module make up to input. BMG module is designed: Have adopted Q =8 soft judgments decipher methods, soft judgment (Q =8) than the hard judgment (Q =2) Encode not gaining more not nearing by 2dB. There is tolerance of 16 branches in all in pair of butterfly type operation; ACS calculates the tolerance of 16 kinds of branches well at first before operation each time. ACS module is designed: In order to raise the speed of deciphers further, merge the single butterfly type operation of two step ACS into a step, construct one pair of butterfly type decipher algorithms, get result of upgrading of two steps of the tolerance of 4 state states at the same time, can save to read and write the number of times in half the memory, the speed of ACS has been raised by one time. Adopt 6 binary digit come operation and store every steps of tolerance; For prevent route from to be that tolerance store to overflow, is it judge , deduct regular method of value to adopt, in order to reduce the number of times compared. Operation is fast, the control circuit is simpler. The bus structure in RAM, can not visit four address units at one time , so we is it cut apart to go on memory, realize single RAM of function with many pieces of RAM of physics. The tolerance in the route stores the design of the module: Use and consider the need of the speed mainly, so that adopted is that the register exchange algorithms. It exchange register algorithm the fast, when the light without being prolonged, last application not high-speed especially, but will bring the increase which consume...
Keywords/Search Tags:wirless measuring, Asynchronism FIFO, viterbi decoder, double butterfly structure, EDA, FPGA
PDF Full Text Request
Related items