The Research And Design For An 8-bit CPU IP Core

With the coming of the communication age, the disadvantage of the traditional SCM (Single Chip Micyoco) was exposed because of its connatural defect of structure. Its speed, scale and performance can't meet the more and more requirements from the users. The technology of System on a Chip (SoC) is widely used in embedded system now for its advantage. In this paper the design methods and the technique of development for SoC is introduced under this circumstance. Furthermore the exploration and research about the design and implementation of an 8-bit CISC (Complex Instruction-Set Computing) CPU on FPGA (Field Programmable Gate Array) are given.The CPU design refers to the Top-Down design method and the modularization ideas from global architecture design to local function implementation. Then it's expounded that how to design data-palh and structure of a CPU by instruction-set. The IP core is divided into three parts, the ALU module, the controller and special registers. ALU is the executing unit that the logical and arithmetic operation are supported; Controller is based on micro-program and state machine, which is used to decode the command and control the executing unit; There are all kinds of registers and MUX in the register module, which is controlled by controller and is the transmission part of datapath. Because of the development of integrate circuit technics.the parallel data and address bus can be implemented in one chip. The architecture enhances the system's performance and speed and predigest the design of schedule.The flip-flop is used to read and write RAM to make instructions can be completed within four clocks . Instruction set is compatible to the industrial standard 8051 microcontroller to ensure applicability, but period of clock which an instruction cycle needs is only the 1/12 of standard MCS51 instruction cycle. The special interface of the address and data is design for RAM and ROM in IP core. The interface and performance can be expanded and enhanced easily because the project is designed by Verilog HDL code.The design has achieved the expected goals in all aspects through the simulation and verification. The CPU core is an important part of SoC, which can be used in many domains, such as control and communication. So the design has its useful value.