Design Of Reusable Viterbi Decoder

Viterbi algorithm is the most likelihood decode algorithm of convolution code. Viterbi decoder means the VLSI implementation of Viterbi algorithm. In the area of communication, convolution code is very popular, so how to improve the performance and reduce the power and area of the decoder is an important thing. In the other hand, different protocols use different convolution code and varied applications have different require for throughput, area and power. So design of reusable Viterbi decoder is important, too.In present dissertation, a radix-4-pipelined state-serial 64-state punctured (4, 1, 6) Viterbi decoder was carried out. By the method of Same Address Write Back (SAWB), we reduced the number of registers to half in contrast with the ping-pong method. We partitioned the memory of Trace Back Unit (TBU) into three parts to decrease the power of read or write operations of memory. The whole module was data-driven, which means the circuit could work under different data rate and avoid those invalid operations. Under TSMC 0.18(m CMOS process, we successfully simulate and synthesize a punctured 64-state (4, 1, 6) Viterbi decoder, which scale without RAM is about 13,757 gates, throughput is 12.5Mbps and estimation of power is about 15mW.Based on this design, a reusable Viterbi decoder was implemented. This decoder adopted the Process Element (PE) technique, which made it easy to adjust the throughput of the decoder by increasing or decreasing the number of PE. SAWB was also implemented. The core parameters, such as the generation words of convolution, the number of PE and the depth of TBU, are all configurable. One program has been developed to generate the Verilog code from these parameters automatically. A decoder generated by this code generator has been successfully simulated and synthesized under the same CMOS process.