The Design And FPGA Verification Of Embedded UART Based On VHDL/FPGA

With the development of the very Large-Scale Integrate Circuit and the deep sub-micron fabricating, System-on-Chip design methodology is becoming the main trend of the Integrate Circuit Industry. As an effective SOC design measure, IP core plays an important role, not only in the SOC industry, but also in the total Integrate Circuit Industry.Universal Asynchronous Receiver Transmitter UART, as a basic input and output system IP core, is generally applied in the SOC system. This paper use Top-down methodology to design and test the designed core by dividing system function. The whole IP core includes sending module, receiver module, interrupt module, Modem module. The whole design is simulated in Xilinx ISE9.1i. The whole process of FPGA verification is introduced particularly. The result proved the design is correct and reliable.There are six sections in the whole thesis. The third, fourth, and fifth sections are emphases of the project, which mainly describe how to design the IP soft core. The necessity of designing the IP soft core of UART is discussed by analyzing the actuality of the IC development. At last, I sum up the works, harvest and what one has learned.