32-bit RISC Microprocessor Module Design

Embeded microprocessor has been applied widely to many kinds of electronic equipments because of its advantages ,such as , high performance, lower power cost and portable characteristic development. Especially, as a strategy, Reduced Instruction Set Computer (RISC) is becoming more popular in the designing of computer architecture. The project implemented a basic architecture of microprocessor on the base of microprocessor general architecture and MIPS32 instruction system.In the project, the microprocessor is composed of integer unit and floating-point unit. The integer unit is designed with five-stage pipeline, including instruction fetch, instruction decode, execution, memory access and write back. The method in designing pipeline, structure hazard, control hazard and data hazard were described in detail in the paper. Different with traditional microprocessor which solves floating-point normalization with soft ware, the project implemented floating-point normalization with hard ware. The research focused on the architecture of microprocessor mainly. According to the task and delay information of the floating-point unit, it was implemented with three-stage pipeline, including pre-normalization stage, calculation stage and post-normalization stage. Approximately, the delay of each stage is equal with each other. Also, floating-addition, floating-subtraction and floating-multiplication can been implemented by the floating-point unit.The integer unit and floating-point unit were described and modeled in VHDL. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of EDA tools, was used in the project. The code was verified in FPGA soft ware environment. Synthesized netlists based on FPGA and ASIC were given in the paper for future work.