The Asic Design Of V5 Interface Between Local Exchange And Access Network

This paper is based on the emphasized developing project of Information IndustryMinistry. This paper studies the hardware realization of V5 interface and aims at ASICdesign and implementation of V5.First, the outline of Access Network and V5 interface is introduced in this paper.On the base of widely research and study, we present the hardware realization schemeof V5 interface (XY990 1) in detail. The chip accomplishes the function of physicallayer and part of data link layer.Several blocks such as ELST, CRC coder/decoder, Bit synchronous digital phaselocked loop and jitter attenuate digital phase locked loop are described in detail.XY9901 is designed with Verilog Hardware Description Language. We use AlteraCPLD Flex 1OK13OE to implement our design. The hardware test of the design ispresented in the end of this paper.