Anti-Radiation Technique Research For Spaceborne Data Processing System

Since the start of the 21th century, Space Engineering has been playing a more important role in the improvement of integrated power for a nation and the new information-based military revolutionary. With technique renovation, the application of VLSI such as FPGA, DSP, SRAM in space-borne equipment is on the increase. Being the key components in space-borne data processing system, FPGA, DSP, SRAM have caught a lot of attention on the influence given by partical radiation in space environment since they were applied. The influence is more serious for the integrated circuit component with higher circuit density, single event effect (SEE) contribute a major part in all the influence. Improveing the ability of anti-radiation for equipment is an inevitable task in space-borne electronic system designing.This paper based on space-borne data processing platform designing, aiming at shielding SRAM and DSP froming the influence of SEE. Analysised the characteristic of malfunction caused by SEE in SRAM and DSP, presented solution to eliminate influence of SEE, then carried out function simulation and testing for the solution. More details are following:(1) Due to the SRAM characteristic that most SEE are sigle bit upset, we proposed coding based Error Detecting and Correcting (EDAC) method to cure the SRAM error in our system. On the basis of analysizing property of several coding type, we concluded the coding type fit out system best is Hamming Code, which can correct 1bit error and detect 2 bit error.(2) Hamming Code is choosed, considering the data stored in our SRAM is 32 bit, we fixed the Hamming Code style match requirement of system reliability is [63, 57] code which has 6 supervising bits. Ensuring correcting ability unreduced, we curtail the 57 information bits down to 32 bits, to make this Hamming Code applicable in our system. And based on this code style, we designed the encoding method on which correcting 1bit and detecting 2 bits function achieved and the structure of EDAC module.(3) Realized EDAC module on FPGA platform through hardware designing with VHDL language, and verified its function by simulation software. According to SRAM chip schedule requirement, we debug the schedule control logic in EDAC module with ChipScope tool, and fixed the optimal schedule setting. We test the EDAC module through DSP programme, the testing result proved that this EDAC module could run unhindered and reliable.(4) For the SEE influence on COTS (commercial off-the-shelf) DSP, based on DSP structure and data flow, we analysized the mechanism of SEE influence in DSP and the result of system caused by fault in data flow. Proposed two solutions: CPU reset method and key variable redundancy, and researched their effect of improving anti-radiation ability of DSP. We proved in theory the key variable redundancy with shortened variable keeping time could reduce data errer probability ideally.The research in this paper based on actual requirement of space-borne information processing system, contained considerable practicability. It could be applied in space-borne equipment of our nation, especially in the civial projects which adopt COTS chips prevalently. Consequentially, it would improve the reliability of our space-borne imformation system in space radiation environment, and make affirmative sense in promoting Space Engineering development of our nation.