Research On SRAM Single Event Upset Hardened Design Based On Bulk Silicon CMOS Process

The fast-growing development of China’s aerospace industry and thus the further exploration of the vast space in the last several years are inseparable from the support of highperformance and high reliability integrated circuit products.The complex radiation environment in space has extremely strict requirements for integrated circuits.In addition,with the progress of device technology,the integration of transistors on integrated circuit chips is becoming higher and higher,which makes the single particle effect on Aerospace chips an important reason affecting the normal operation of aerospace.SRAM cell is an important part of the chip and occupies the largest area of the circuit.It is necessary to design the anti radiation reinforcement of the memory cell.Based on 65 nm CMOS technology and polarity reinforcement technology,a storage unit with anti radiation performance RHMC-12 T is proposed and simulated.In addition,several reinforcement methods of traditional inverter are studied and verified by simulation.Firstly,the intolerance of storage nodes of traditional 6T SRAM cells to single event effect is analyzed,and then the common reinforcement methods of SRAM cells are briefly introduced.Then,the key charge of 6T SRAM unit and the anti SET reinforcement method of inverter are studied,analyzed and verified by simulation.Use the simulation software TCAD to simulate the circuit,The results show that the pulse width of SET can be effectively reduced by increasing the size of NMOS tube.In addition,the pulse width of SET can be effectively reduced by using source isolation and reinforcement technology and changing the connection mode of transistors in inverter,such as series or parallel PMOS transistors and series NMOS transistors.The research on the anti SET reinforcement method of inverter in this dissertation has certain guiding significance for the research and design of SRAM cell with anti radiation performance in the future.Finally,based on the polarity reinforcement technology,an anti radiation storage unit named RHMC-12 T is proposed to resist the single event effect.The unit reduces the number of sensitive nodes by surrounding the storage nodes with all PMOS transistors.In this way,the anti radiation performance of the unit can be further enhanced by reducing the probability that the storage unit is overturned due to the bombardment of high-energy particles,as well as optimizing the layout of the storage unit.Simulation software Cadence is used to verify the storage unit,and the results show that the proposed storage unit has good radiation resistance.Compared with Quatro unit,the reading speed of RHMC-12 T unit is increased by 24% and the Hold static noise tolerance is increased by 14%.Compared with several kinds of anti radiation storage units,in this dissertation,the storage unit proposed has its own advantages,with the feature of fast reading and writing speed as well as good stability.