Simulation And Analysis Of Single Event Transient On SRAM

With the continuous development of integrated circuit manufacturing technology and the continuous development of the aerospace industry,the impact of Single Event Effects on integrated circuits is becoming more and more serious.SRAM is widely used in integrated circuits due to its high level of integration and speed.One of the main problems of the aerospace chip failure is the failure of the SRAM caused by the Single Event Effect.In addition,the Single-Event Effect test has the problems of stress,difficulty in queuing,high cost and so on.Therefore,it is of great significance to study the Single Event Effect simulation method of SRAM and use the simulation method to replace the experiment.In this paper,the transient currents generated by high-energy particles of different LETs at 130 nm entering the sensitive region of the semiconductor device are studied firstly.A three-dimensional model of the semiconductor device was built using tools such as Cogenda's Visual TCAD.High-energy particles with different LET values were incident at a vertical angle in the sensitive area.Transient current source models of 26 different LETs from 0.4 to 100 were obtained.The paper adopts the method of scanning analysis to analyze the sensitivity of single-event transient effects on the key signals of SRAM.First,according to the working mechanism of SRAM,the key signals in the SRAM are extracted and the susceptible locations susceptible to Single Event Transient effects are analyzed.For each key signal,a scanning analysis method is used at the sensitive position to scan the different injection times of the current source and the sensitive position corresponding to different LETs,and finally to obtain the minimum LET value of each circuit in the sensitive position that can cause the circuit to fail,that's the sensitivity of the key signal.The analysis results show that the key signals in the column decoder and the sensitive amplification module are most sensitive to the single-event transient effect,the logic circuit module is the second,and the row decoder module is the least sensitive.In this paper,Single Event Upset threshold analysis and cross-section simulation analysis were performed for SRAM memory cell modules.There pose of the memory cell at different process angles,different temperatures,and different voltages was analyzed and the Single Event Upset LET threshold was obtained.The simulation results which is 0.6 Me V·cm2/mg were consistent with the reference.In the cross-section simulation,the random nodes in the randomly selected memory cells are injected by a current source with random pulses a certain range at random times.Each LET value is simulated for an average of 100 times,and flipping is performed at different LET values.Sections were fitted with the Wei Bull function to fit the inverted section curve is 1.6×10-8 cm-2/bit,and the saturated cross section obtained by fitting was kept in the same order of magnitude as the experimental data which is 1.6×10-8 cm-2/bit.This paper also analyzes the Single Event Transient of SRAM peripheral circuits.Using a random fault current injection method that selects circuit random nodes,random fault injection time,current sources that pulse peaks and widths within a certain range of random,the simulation takes 100 average values.The paper statistically analyzes the SRAM logic circuit module,row decoder module,column decoder,sensitive amplifier circuit module and the all peripheral circuit.The ability of the peripheral circuit to resist single-particle ability with LET and the capability vs.clock period curve were obtained to evaluate the ability of the peripheral circuit to resist Single Event Effects.The analysis results show that with the increase of the LET value and the increase of the clock frequency,the errors in the peripheral circuits are gradually increased,but the trends of the different peripheral circuit modules are different.