| Discrete-time Δ∑ ADC which can achieve high resolution by oversampling and noise shaping is a widely used architecture in a broad range of applications,such as Internet-ofThings(IoT),industry,healthcare,and scientific systems,especially when the high resolution or high dynamic range is a critical demand.Most of these applications are powered by batteries or energy harvesters,so high energy efficiency is required.Nevertheless,it always needs a high-performance OTA-based integrator that heavily draws static currents and scales with unfriendly operation frequency.Traditional amplifier structures require a large amount of static current consumption,which is correspondingly low energy efficiency and difficult to fully dynamic design.Therefore,it is challenging how to make high-precision Δ∑ ADC fully dynamic with bandwidth/power scalable,which is also a hot research topic at present.This dissertation mainly focuses on the research and design of the fully dynamic Δ∑ADCs.Through the continuous optimization and improvement of the traditional floating inverter amplifier(FIA),multiple amplifier topologies are proposed and used in the different architectures of discrete-time Δ∑ ADCs,and finally,high resolution and high dynamic rangeΔ∑ ADCs realize the fully dynamic operation.To enable Δ∑ ADC scaling with the sampling frequency fs on the fly,the capacitively biased swing-enhanced floating inverter amplifier(SEFIA)is proposed.Swing enhancement and fs-adaptive self-biasing of SEFIA are achieved with only switches and capacitors,thereby preserving the power efficiency and the fully dynamic nature of FIAs and enabling duty-cycled operation with simple clock gating.Finally,the 3rd order 1-bit Δ∑ ADC,employing the proposed SEFIA-based integrators is implemented in a 180 nm CMOS process.This is the first power/bandwidth scalable Δ∑ ADC.Measurement results show that it achieves a consistent performance of>87 dB SNDR over 4× clock frequency scaling.when the supply and reference are varied together from 1.3 to 1.8 V The SNDR remains above 87 dB.The prototype ADC only consumes 4 μW when operating with an oversampling ratio of 125 and 800 Hz signal bandwidth.The fully dynamic Δ∑ ADC achieves a DR of 94.1 dB and a peak SNDR of 89.3 dB,leading to a Schreier figure-of-merit of FOMDR of 177.1 dB and FOMSNDR of 172.3 dB.Compared with single-loop Δ∑ ADC,the MASH structure enhances the effect of noise shaping by sending the quantization error of the previous stage to the next stage,and the stability of the system is mainly determined by the stability of each stage structure.Therefore,the design of full dynamic MASH ADC is suitable for applications with higher accuracy and dynamic range.However,the high dc gain of amplifiers used as the first integrator is required in MASH ADC.The CLS technique is proposed to employ in the FIAs to boost the equivalent dc gain of the FIAs.Meanwhile,the dynamic body-biasing technique with a single capacitor is used to assist the level-shifting operation of the amplifier.Considering that the MASH ADC certainly requires the linearity of the amplifier,and the output swing of FIA is limited,the coefficient of ADC is scaled to meet the design requirements.Finally,the fully dynamic MASH ADC is implemented in a 55 nm CMOS process.The total current when operating at 250kHz fs consumes 2.4μA at a supply of 1.2V,with the digital circuitry(DWA,SAR logic,and clock generator)consuming 30%,while the analog parts(integrators,comparators,and the reference)consume 70%of the total power.At 1kHz bandwidth,the prototype achieves 96.9dB DR,94.0dB SNDR,and 99.8dB SFDR,leading to a Schreier figure-of-merit of FoMDR of 182.3dB and FoMSNDR of 179.4dB.To further extend the scalability in bandwidth and power consumption of highresolution ADCs,the zoom ADC is a better choice,which combines the advantage of SAR ADC and Δ∑ modulator,to achieve high resolution and high energy efficiency simultaneously.Considering that the transconductance(gm)of the SEFIA,suitable for scalability,is proportional to the clock frequency(fs),the improved SEFIA adopts the CLS technique to shield the output swing with respect to the variation of fs,which improves the scalability of the proposed SEFIA.One stage of the improved SEFIA using the CLS technique is presented,simultaneously achieving both high gain and high output swing.Finally,a 1250×bandwidth/power scalable fully dynamic discrete-time(DT)zoom ADC based on the improved SEFIA with CLS is presented,which scales power from 453nW to 122μW by only changing fs,and the proposed ADC,with near-constant energy efficiency,simultaneously achieves high resolution(>95.2 dB)and high dynamic range(>96.7 dB)during the scalable bandwidth.At 5kHz BW,it achieves 97.3dB DR,96.3dB SNDR,and 112.2dB SFDR,leading to FoMDR of 177.1dB and FoMSNDR of 176.1 dB. |
