Research And Design Of Low Power Wide Bandwidth Scalable Range ΔΣ ADC

In today’s society,the growing prosperity of the Internet of Things market makes sensors increasingly popular in human production and life.ADC,as the core module of a sensor,has received extensive attention and research.People also put forward higher requirements for the ADC,such as low power consumption,high precision,PVT stability,and scalable bandwidth.Due to the oversampling and noise shaping,ΔΣADC can significantly reduce the in-band quantization noise and achieve the requirement of high precision.Therefore,it is widely used in medium and low frequency and high precision occasions.According to the different performance requirements of sensors in the Internet of Things,this thesis researches and designs a low power,high precisionΔΣADC with wide bandwidth scalable range by using the dynamic operational amplifier.In this thesis,the low distortion second order cascade of integrators with feed forward architecture is adopted,and the voltage summation block is combined with a3bit asynchronous SAR quantizer to provide sufficient signal-to-noise ratio for the ADC.At the same time,according to the actual circuit structure,an improved DWA module is used to suppress the mismatch between DAC capacitors caused by multibit quantization.In order to further improve the precision,technologies like autozeroing,non-overlapping clock and bootstrapped switch are also used in the system.In the critical amplifier design,by introducing cascaded triodes into the swing-enhanced floating inverting amplifier,the amplifier reaches the DC gain of 60d B while also keeping a large output swing.Moreover,the full dynamic characteristic of the amplifier eliminates static current,greatly reduces power consumption,and becomes the basis for the ADC to realize the scalable bandwidth.The circuit design and layout drawing of the proposed ADC are implemented in TSMC 55nm CMOS process,with core area about 0.24mm~2.The chip is powered by a1.2V supply and the sampling frequency is 200k Hz,corresponding to 800Hz signal bandwidth.Post-layout simulation results show that the SNDR of this ADC is 95.87d B under a 207.5Hz,-2d BFS sinusoidal signal,and the power consumption is 2.51μW,resulting in an SNDR-based Schreier Fo M of 180.9d B.The DR of this ADC is 96.5d B,corresponding to a DR-based Schreier Fo M of 181.5d B.At the same time,this ADC has good PVT stability.And the ADC performance remains stable when the sampling frequency varies from 10k Hz to 800k Hz,signal bandwidth varies from 40Hz to 3200Hz correspondingly,achieving an 80 times wide bandwidth scalable range.