| Almost all earlier high speed ΣΔ modulators with MHz signal bandwidth are implemented with switched-capacitor circuit techniques. Whereas ΣΔ modulators with continuous-time loop filters have the advantages of lower power consumption and intrinsic anti-alias filtering. Moreover, because the sampler of a continuous-time ΣΔ modulator is right in front of the quantizer inside of the noise shaping loop, any sampling error at signal frequencies is greatly suppressed by the high gain of the loop filter together with the quantization noise. Thus key non-idealities associated with the front-end sampling network in SC modulators are avoided. Prior implementations of continuous-time ΣΔ modulators in CMCS have either narrow bandwidth (200-kHz bandwidth with 82-dB dynamic range [1]) or limited dynamic range (2-MHz bandwidth with 70-dB dynamic range [2]) due to architecture level limitations.; This dissertation presents the design and experimental results of an 88-dB dynamic range 1.1-MHz input signal bandwidth continuous-time ΣΔ modulator for ADSL applications. The proposed ΣΔ modulator architecture and circuit design techniques could be easily applied to other wireless or wireline communication applications. Highlights of the proposed architecture include: (i) Multi-bit quantization is deployed to significantly improve resolution and bandwidth. (ii) NRZ feedback DAC pulse shaping and multi-bit quantization are utilized to effectively reduce clock jitter sensitivity. (iii) Excess loop delay problem of conventional continuous-time ΣΔ modulators is eliminated. (iv) A sound continuous-time noise shaping loop filter design with discrete-tunable capacitors achieves a high and stable SNR of less than 2 dB over large (such as ±50%) process variations.; A 3rd-order continuous-time ΣΔ modulator with 5-bit internal quantization was realized in a 0.5-μm double-poly triple-metal CMOS technology, with a chip area of 2.4 × 2.4 mm2. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR (Signal/(Noise+Distortion) Ratio) over 1.1-MHz signal bandwidth with an over-sampling ratio of 16, dissipating 62 mW from a 3.3-V power supply. Our work improves signal bandwidth by 5.5 and 11 times compared with prior publications with similar dynamic range performance [1, 3]. Clock jitter sensitivity is improved by around 33 dB over prior work [1] as simulated and calculated. |
