Design And Implementation Of Mm-wave CMOS Frequency Synthesizer

Millimeter wave(mm-Wave)band has great potential for 5G mobile communication and radar applications in the future because of its high operating frequency and rich spectrum.With the development of CMOS process,it has advantage of high integration,low cost and power consumption,and it is highly desired to realize mm-Wave communication and radar systems in CMOS process.As the key building block of the wireless transceiver,the phase-locked loop(PLL)based frequency synthesizer directly affects the system performance whose performance affects that of the wireless transceiver.Accordingly,the mm-Wave integrated PLLs are designed and implemented with CMOS process in this thesis.The main contents and contributions of this thesis are summarized as follows:1.In terms of building blocks,based on passive transformer resonator network this thesis presents three low phase noise VCO topologies.They are:a)a VCO based on capacitive-spliting and transformer feedback techniques.This VCO enhances the g_m of the cross-couple pair and the quality factor of the resonator at the operation frequency,achieving high output swing.Its tuning range is 25.7-29.7 GHz.The measured phase noise is about-130 dBc/Hz at 10 MHz offset;b)a transformer feedback VCO bwith the power-ground interconnect inductor and embedded decouple capacitor.The second harmonic real impedance is achieved at the VCO cross-couple pair source terminal.Accordingly,the common-mode current path is reduced and the signal symmetry improved,suppressing the flicker noise up conversion.Its tuning range is 28.5-36.2 GHz and FoM_T is-193.6 dBc/Hz;c)a VCO based on drain-to-gate transformer feedback technique for 60 GHz application.This VCO improves start-up reliability,output signal swing and phase noise.Its tuning range is 59.8-65.4 GHz.At 61.3 GHz,the proposed VCO achieves low phase noise of-94.9 dBc/Hz at 1 MHz offset and-118.4 dBc/Hz at 10 MHz offset,respectively.Moreover,to improve the LO phase noise performance to realize the frequency multiplying PLL topology for the transceiver system,this thesis presents a low-power wide bandwidth injection-locked frequency tripler(ILFT)with injection current enhancement techniques.Based on the transformer passive network,the phase response of the tripler is relatively flatten at 0 degree.With the tail filter of the injection transistors,the injection current of the tripler is significantly increased,thus achieving the injection locking range of 31.5-40.5 GHz,with the core power consumption only 7.2 mW.2.For communication systems,three PLLs are presented with 100 MHz reference signal.They are:a)a wide bandwidth charge-pump PLL(CP-PLL),which achieves 7.8-31.2 GHz tuning range.The measured phase noise is-100 dBc/Hz and-100 dBc/Hz at 100 kHz and 1 MHz offset from 16GHz output frequency,respectively;b)a sub-sampling PLL(SS-PLL),which achieves 15-20 GHz tuning range and realizes only-38 dBc integrated phase noise(IPN)at 16 GHz output frequency.The measured phase noise is-103.7 dBc/Hz and-105.2 dBc/Hz at 100 kHz and 1 MHz offset,respectively;c)a reference-sampling PLL(RS-PLL),which also achieves 15-20 GHz tuning range.The measured phase noise is-98.2 dBc/Hz and-95.5 dBc/Hz at 100 kHz and 1 MHz offsetfrom 16GHz output frequency,respectively.In terms of performance comparison and analysis,the CP-PLL achieves the best spur and good IPN performance;the SS-PLL achieves the best in-band phase noise and IPN,but its spur performance should be improved further;the performances of the RS-PLL are in between that of the CP-PLL and the SS-PLL.3.For frequency-modulated continuous wave(FMCW)radar systems,this thesis presents a 32GHz frequency modulated continuous wave(FMCW)modulator based on the CP-PLL with nested sub-PLL structure.With the sub-PLL,the low-pass effect in phase domain is realized,reducing the noise folding effect,noise and spurs due to the delta sigma modulator(DSM).The measurement results illustrate that in fractional-N mode,the nested-PLL achieves the phase noise of-91 dBc/Hz at 1MHz offset frequency and the fractional spurs of less than-54 dBc at 30.78 GHz output frequency.In FMCW mode,the proposed modulator achieves a triangular chirp with 1.08-to-2.16GHz bandwidth at about 32 GHz center frequency.And the measured root mean square(rms)frequency errors of 400 kHz and 770 kHz are achieved with the ramp slopes of 1.08 GHz/93?s and 2.16 GHz/93?s,respectively.Measurement results prove the improvements of the phase noise and chirp linearity with the sub-PLL.