Research And Realization Of Shielded Gate Trench Power MOSFET With Low Dissipation And High Reliability

Power MOSFET device plays a key role in power system.Traditional power MOSFET device has a large loss,which affects the overall efficiency of the system.Since the 1990 s,with the advent of Super-Junction(SJ)power MOSFET theory and products,the conduction loss of high-voltage power MOSFET has been greatly improved.However,due to the limitation of theory and technology,Super-Junction power MOSFET has no advantage in the medium and low voltage ranges.The emergence of Shielded Gate Trench(SGT)structure has brought great opportunities for improving the performance of medium and low voltage power MOSFET devices.The SGT structure has the advantages of low on-state resistance,fast switching speed,large safe operation area(SOA)and miniaturized encapsulation.The SGT power MOSFET product owns broad market prospects in green household appliances and energy-saving systems.However,there are still some difficulties in the design of SGT power MOSFET devices at present:(1)Conventional terminal design method is not enough to ensure breakdown voltage of the terminal as excellent as that in the cell area at the vertical cell stripe direction and the corner.(2)The output loss of the device is large due to the extra drain-to-source capacitance induced by the source polysilicon.(3)During the switching-off section,there is electric potential distribution existing in the source polysilicon along the cell stripe direction,which makes the appearance of weakness point in the device.This weakness point is the main reason for the failure of the device during Unclamped Inductive Switching(UIS)process under high current and high voltage stress.Based on the charge balance theory,the electrical performance of SGT power MOSFET device is improved from the aspect of 3D terminal design and drainto-source capacitance optimization.Based on the failure mechanism,the method of increasing the contact density of source polysilicon is proposed to eliminate the weak points,and the improvement effect is strengthened in the layout.Finally the sample with low dissipation and high reliability has been fabricated.The main innovations of this paper are as follows:1.A 40 V SGT power MOSFET with upper/lower structure is researched and fabricated.The breakdown voltage of the device is 44.7 V and the on-state resistance is 1.7 m?.On this basis,a novel NPN sandwich source polysilicon structure is innovatively proposed.The simulation results show that the drain-to-source capacitance of the device is reduced by 51%.2.A 120 V SGT power MOSFET with left/right structure is researched and fabricated.The terminal structure of the device is designed by 3D technology to ensure the breakdown point of the device is located in the cell area.The breakdown voltage of the device reaches 125.4 V and the on-state resistance is 3.8 m?.In addition,the the PN junction capacitance structure and the NPN sandwich source polysilicon structure is introduced into the source polysilicon,which reduces the drain-to-source capacitance of the device by 64% according to the simulation results.3.The failure mechanism of SGT power MOSFET in UIS process is revealed.There is a step distribution of potential existed in the source polysilicon along the direction of the cell stripe,which destroys partial charge balance of the device and leads to the failure of the device due to current concentration.On this basis,a method of increasing contact density of the source polysilicon is proposed to improve the UIS rubustness of the device.The test results show that this method can improve the UIS ability of 100 V SGT MOSFET from 729 m J to 1482 m J,without sacrificing other electrical characteristics.