Method Of Reliability Design And Modeling For Very Deep Submicron Integrated Circuits

The density and complexity of VLSI is increasing continually with scaling down of design rules in order to meet the demand of performance of SoC (System on Chips). It was became an important issue that how the long-term operation reliability of complicated SoCs is evaluated. Since long-term operation reliability of VDSM CMOS circuits is determined by microcosmic fault mechanism of MOSFETs, evaluation and improvement to reliability of CMOS circuits should be based on analysis of fault pattern and well understanding to basis physical fault mechanism of MOSFETs.In this thesis, analysis and modeling of the several dominant reliability degradation mechanisms impacting reliability of VDSM devices was made, and system of evaluation algorithms for circuit reliability degradation under AC stress was built. Moreover, through designing software architecture of semiconductor IC reliability evaluation platform, all the evaluation algorithms were integrated into a platform system, which is implemented in Cadence IC design tools.This thesis first introduce basis feature of VDSM MOSFET, BSIM3 device model describing MOSFET's behaviors and principle of circuit simulation analysis, as well as framework of Cadence IC design tools. And then, analyses and model degradation reliability mechanism of VDSM MOSFET devices. The three dominant ones that is HCI (Hot Carrier Injection effect), NBTI (Negative Bias Temperature Instability), TDDB (Time Dependence Dielectric Breakdown) were researched, and their degradation and current models which were able to evaluate degradation and lifetime of devices were given. Based on it, some quasi-static models for forecasting degradation of devices under operative circuits is given too.Basing on the three degradation models, the methods of circuit reliability simulation is given. In this thesis, the simulation algorithms applying to digital or analog circuits for evaluating long-term operation lifetime is presented, which is used to predict overall degradation and lifetime of CMOS circuits under long-term working condition. This method has been implemented in Cadence design environment. And more, a degradation model of MOSFET drain current,ΔI_d model, is proposed for simulating working waveform of degraded circuits under HCI stress. The model is depicted with single compact equation and is derivative in all three working regions. With all these algorithms, device-level circuit reliability simulation is finished basically.This thesis proposed a method of Multi-Target Global Optimal Parameters Extraction for reliability model parameters. In this way, the parameters of several models under the same bias condition can be extracted synchronously. The extracted results not only make the models using them meeting measured very well, but can take the intrinsic relationship among these parameters into account. It has acquired good effect that applys this method to reliability parameters extraction tools named OPTIMRel.At last, a VDSM Integrated Circuit Reliability Simulation Platform has been designed. In this part, software architecture of reliability simulation platform is designedd first, and some common demands in the fields of Si MOSFET devices and circuits reliability research were taken into account making the platform meeting most of application in this domain. Then, design and implementation of the reliability algorithms integration was given. With the software architecture, "Xi'dian University Integrated Circuits Reliability Analysis System", for short XDRT system, was achieved. It provides a platform for research of VDSM MOSFET circuit reliability, and also became the basis of circuit reliability research in the future.