Investigation On Reliability Of 650V GaN-on-Si Power Devices:Mechanisms And Characterizations

650 V GaN-on-Si HEMT devices have achieved rapid development in the past few years and have been widely used in fast charging,wireless communication and other fields.In this thesis,we investigated the reliability of GaN HEMT devices specifically in high temperature and high voltage applications.First of all,the dielectric degradation induced device threshold voltage(Vth)shift was investigated.High temperature reverse bias(HTRB)stress tests were applied to study the shift of Vth under high electric field stress and its degradation mechanism.It was found that electric field induces negative Vth shift by causing electron de-trapping in the dielectric layer.High temperature constant current(HTSC)stress tests were supplied to study the hot carrier injection induced Vth shift.It was found that the constant hot current induces positive Vth shift by injecting hot electrons in the dielectric layer under gate.We proposed a novel hard-switching high temperature reverse bias(HS-HTRB)stress test to study the Vth shift caused by the hot electron pulses introduced in hard-switching operations.It was found that the hot electron pulse induces a slight negative shift of Vth through impact ionization in the channel with high electric field at low temperatures,as temperature rises,the hot current pulse shifts Vth positively by hot electron injection.Furthermore,the temperature dependence of the above degradation mechanisms were also studied.Secondly,the buffer deep-level electron trapping induced degradation of Vth and on resistance(Ron)were investigated.By performing HTRB and HS-HTRB stress tests on devices with different substrate status,the impact of deep levels in the buffer layer on the Vth shift was studied.It was found that electron injection into the buffer layer induced by vertical stress would cause positive Vth shift and sub-threshold swing(SS)degradation.The electron trapping mechanism in buffer layer under different electric field directions was investigated by high temperature vertical stress tests.By performing the vertical stress tests at different temperatures,the activation energy of the deep-level trapping centers in the buffer layer which cause the device Ron degradation was calculated.The defect types and their distribution in the epitaxial structure of HEMT device were investigated by analyzing the vertical leakage of the under stresses.Thirdly,we investigated the structure of cascode HEMT and its failure mechanism.By analyzing of the internal structure of cascode device,we proposed a novel test method with higher efficiency and accuracy to determine the specific failure location of the cascode device after stress.This method keeps the traditional test process within only three steps,which greatly improved the efficiency of cascode failure analysis.By performing HTRB stress tests on cascode devices at different temperatures and different stress voltages,the activation energy that causing device Ron degradation was calculated.It was also found that the failure mechanism of the device was changed as the stress voltage increased.Finally,we performed the accelerated aging experiments and made lifetime prediction on the cascode devices.Through both voltage acceleration and temperature acceleration experiments,the voltage acceleration factor and failure activation energy(Ea)of the device were determined,respectively.By analyzing the lifetime distribution of devices,the failure model and failure mode of the device were determined,and the lifetime of the device in application condition was predicted.