Numerical Research Of Thermal Resistance And Thermal Reliability Tests Of Diecrete Power Device Packages

Power semiconductor devices are inevitably faced with frequent turn-onand turn-off processes. Power dissipation generates considerable heat, whichcould only dissipate through package. To avoid excessive junction temperatureinduced failure, thermal management and reliability standards of power devicepackages are stricter than IC devices.Firstly, according to JESD51-1and JESD51-2A, experimental research ofDiscrete high power packages: TO-220FP, TO-247, TO-3P Junction-to-ambient thermal resistance is conducted and optimized. Temperature sensitiveparameter (TSP) of both IGBT and Power MOSFET devices are calibrated.FloTHERM based computational fluid dynamics (CFD) simulations areutilized to judge the thermal performance of these packages with the samematerial properties. Simulation results match experimental data well with littleerror, which means our test system is reliable.In addition, to study the effect of temperature changes on discrete powerpackage structure, finite element method (FEM) simulations of temperaturecycling and thermal shock test is applied to analyze the internal stress andstrain. Static structural analysis and sequentially coupled thermal-structuralanalysis are adopted. Impact of different die size, solder materials and packagedefects are considered for design of experiments (DoE). Package defects willcause change of internal stress distribution, which is hidden trouble that maylead to failure at temperature cycling test. Reduction of chip thickness resultsin lower maximum stress and plastic strain of solder layer during thermal shocktest. Conventional high lead content solder, whose deformation resistance islower than lead free solder, gains more plastic strain accumulation and lower thermal fatigue life.