Test methodology for SRAM based FPGAs

This thesis addresses the development of a test methodology that allows fault detection and localization in logic and routing resources of coarse grained SRAM FPGAs. Furthermore, the test methodology is intended to address a broad range of architectures and device sizes. The testing of an SRAM FPGA involves the testing of logic and routing resources. A test approach for logic resources is presented that allows full functional fault coverage of Configurable Logic Blocks (CLBs) through use of specialized test configurations. These CLB test configurations and their test vectors were developed for the XC3000 and XC4000 devices. A methodology is presented whereby multiple CLBs in a device can be exercised in parallel with the above test configurations. Algorithms for dynamic generation of device configurations are presented that allow the test approach to be applicable to a broad range of device architectures and sizes. The algorithms were implemented and the resulting software was tested for the smallest and largest devices in both the XC3000 and the XC4000 architectures, thereby demonstrating the flexibility of the methodology. (Abstract shortened by UMI.).