Design and characterization of CMOS integrated synchronous oscillators

This dissertation addresses design and characterization of CMOS integrated synchronous oscillators (SO) and a modified Phase-locked Loop using an injection locked SO, which is identified by Coherent Phase-locked Synchronous Oscillator (CPSO) in this document. The motivation of this research is to make further explorations of the injection lock phenomenon on the basis of early research work and apply the developed theory in designs of novel integrated synchronisation circuits for high speed digital/analog micro-chip implementation. The theoretical part of this work includes an AC equivalent circuit analysis of a modified Colpitts oscillator which yields a differential equation describing the SO injection locking operation. This equation is solved using an orthogonal technique, deducing a SO differential phase equation. The SO differential phase equation is studied for both the injection-and-locked and the injection-but-unlocked cases. The SO phase acquisition process, under the injection-and-locked condition, is described by an analytical expression. The output spectrum of an injection-but-unlocked SO is formulated in a closed form, which is fully supported by experimental observations. A transient analysis of the CPSO system is performed using a "phase plane" technique. Based upon the SO phase equation and the transfer characteristics of the loop components, a second order phase equation is derived. This equation is graphically presented on a phase plane using an "analog computer". An analytical formulation describing the propagation delay time of a CMOS inverter is developed. The model includes both the intrinsic delay, which is the time for carriers to travel through the channel of a MOSFET, and the extrinsic delay, which is the time to charge (or discharge) the load capacitor to a threshold voltage level so that the following gate is able to change its state. This model provides a good prediction of the CMOS SO oscillation frequency.