Integrated RF CMOS frequency synthesizers and oscillators for wireless applications

PLL (Phase-Locked Loop) frequency synthesizers are used in wireless transceivers for frequency conversion. Recent directions in PLL frequency synthesizer research and development are to fully integrate PLL synthesizers in CMOS technology, to improve phase noise performance, and to operate wide range of frequency bands and channel bandwidths. Fully integration of synthesizers in CMOS technology is desired for low cost, low power consumption and small size in mobile wireless terminals. Low phase noise and high performance are required by digital modulation techniques which have been used in new generations of wireless standards for the efficient use of available frequency spectrum. Operation over a wide range of frequency bands and channel bandwidths are required to support migration and backward compatibility in the wireless standard evolution. This work explores wideband PLL frequency synthesizer design and implementation in CMOS technology with focus on integration of wideband VCOs (Voltage-Controlled Oscillators).; Phase noise of a PLL synthesizer is a major design consideration and integration issue. A PLL noise model is developed for noise optimization purposes. A SPICE implementation of the PLL noise model is presented and used in the design and optimization of PLLs for broadband wireless applications.; Wideband RF VCO design with sub-bands is investigated. Frequency planning, synthesizer architecture and technology considerations for integration are also explored for wideband VCO design. Band switching techniques for VCO tuning range are presented. Active VCO circuit topologies and resonator design are also presented.; Wideband PLL frequency synthesizers are designed and implemented for a multi-band/standard IEEE 802.11a/b/g WLAN radio in 0.18μm CMOS. Phase noise trade-offs for PLL design are explored in this application. Loop filter design in an integrated environment is also investigated. Development and design of a wideband VCO for this application is also presented. An auto calibration circuit is developed for the VCO tuning band selection.; Another application of the wideband PLL frequency synthesizer is designed and implemented for a fully integrated dual-mode frequency synthesizer for GSM and WCDMA standards in 0.5μm CMOS. A hybrid integer-N/fractional-N architecture is developed to meet the multi-standard requirements. A dual-band VCO is developed for this application.; Design and implementation of high performance RF VCO depends on the RF models of the devices. RF CMOS characterization and modeling techniques are explored. Microwave wafer measurement and calibration techniques are also investigated for CMOS technology. A test chip is developed in 0.5μm CMOS technology. CMOS technologies are evaluated for RF design.