| The implementation of high-performance integrated phase-locked loops (PLLs) represents one of the primary design challenges in integrating a complete wireless RF transceiver into a single chip.;In this work, we explore the design trade-offs to achieve high-performance for fully integrated RF CMOS PLLs. Based on investigation at system-level, critical design parameters are chosen to achieve low phase-noise, fast settling behavior, and low power consumption. New circuit blocks and design techniques are presented. A novel dynamic phase-frequency detector is proposed which demonstrates no visible dead-zone, extended phase-detection range, and high frequency operation. Programmable charge-pump techniques are proposed to improve system performance in terms of loop dynamics and spur reduction. Optimization techniques for fractional-N control are also discussed. With the adoption of a state-of-the-art 0.18 mum Cu CMOS technology, high-speed dynamic-logic frequency dividers, and high-Q on-chip spiral inductors are obtained. The design techniques and high-performance circuit blocks are then applied to the design of a fully integrated 5.8GHz PLL for WLAN applications. |
