Investigation of a multi-GHz single-chip CMOS PLL frequency synthesizer for wireless applications

In this dissertation, the feasibility of implementing an integrated Phase-Locked Loop (PLL) CMOS Frequency Synthesizer (FS) is discussed. The most challenging part in the loop is the integrated Voltage-Controlled Oscillator (VCO). To achieve low phase noise, the quality factor (Q) of an on-chip resonator consisting of inductors, varactors and transistor parasitics must be improved. Through a layout optimization, Q of >140 at 5.5 GHz and >40 at 26 GHz for MOS capacitors have been achieved. Q of 57 at 5.5 GHz for a pn-junction diode which is sufficient for varactor applications has been measured while Q of 57 at 1.1 GHz for transistor parasitics has also been achieved.; A modified negative-resistance oscillator topology which utilizes only PMOS transistors is developed. Using this oscillator topology for a 1.24-GHz VCO, phase noise of --137 dBc/Hz at a 3-MHz offset which meets the Global System for Mobile Communications (GSM) requirement has been measured. Additionally, by using an inductor structure incorporating a spiral inductor and package parasities, a 1.1-GHz 13-mW VCO with extrapolated phase noise of --140 dBc/Hz at a 3-MHz offset is demonstrated. These phase noise results are the lowest reported to date for 1-GHz single-stage CMOS VCOs. To improve the power supply rejection ratio for the modified VCO topology, a bias circuit has been designed and integrated with 5.5-GHz VCOs. Phase noise of these integrated VCOs is --117 dBc/Hz at a 1-MHz offset which is the lowest phase noise reported to date for 5.5-GHz CMOS VCOs. To investigate the capability of CMOS technologies, an LC oscillator operating at 25.9 GHz is also demonstrated in a partially scaled 0.1-mum bulk CMOS process. Currently, the 25.9-GHz VCO is the CMOS circuit with the highest operating frequency.; Finally, an integrated 5.5-GHz PLL FS implemented in a 0.25-mum CMOS process is demonstrated. To reduce switching noise, the prescaler is designed using a source-coupled-logic structure. The prescaler has a fixed division ratio of 128 and consumes only 4.1 mW at 5.4 GHz. A new charge pump circuit is developed to reduce the current glitch at the output node while maintaining a sufficient switching speed. By incorporating a voltage doubler and level shift circuits with the charge pump, the VCO input voltage range is increased from 1.3 to 2.5 V with immeasurable phase noise degradation to the PLL. The phase noise of the FS is lower than that of the free running VCO by >50 dB, at a 1-kHz offset, and the spurs are >63 dB below the carrier. The experimental results suggest that a CMOS FS operating above 5.5 GHz with adequate performance for high-bit-rate applications is feasible.