A high-speed parallel pipeline A/D converter technique in CMOS

The key objective of this work is to achieve the maximum possible A/D converter throughput, with reasonable power and area, in CMOS. This research proposes a new architecture for high-speed A/D conversion in CMOS consisting of a parallel time-interleaved array of pipelined A/D converters (ADC's): a parallel pipeline array. The work builds on and combines two existing concepts in A/D architectures: (a) pipelined multistage ADC's and (b) parallel time-interleaved converter arrays.; A major portion of this dissertation is devoted to a detailed review and exposition of the operation of pipelined multistage ADC's at both the algorithm/dc transfer characteristic level and the implementation level. Error sources and nonidealities are discussed, with particular focus on switched-capacitor (SC) approaches. A generalized approach to analysis of multistage A/D conversion is described, which is applicable to a large class of ADC architectures.; Performance limitations for parallel pipeline ADC's fall into two main categories: (i) problems associated with the use of parallelism and (ii) problems associated with the limited speed of the individual channel.; A major problem associated with the use of parallelism is that the hardware cost increases in direct proportion to the number of parallel paths. In order to keep power and area reasonable to facilitate implementation on a single IC, key resources such as resistor strings, bias circuitry, and clock generation circuitry are shared over the array. Another important issue is the difficulty of path matching in the analog domain. Offset, gain, and timing mismatches between the multiple channels give rise to fixed pattern effects, which in the frequency domain are manifested as spurious harmonics. These tones occur at multiples of the individual channel sampling frequency, in the case of offset mismatch, and as sidebands around multiples of the channel sampling frequency, in the case of gain and timing mismatches, respectively. A review of the effects of these inter-channel mismatches at the signal processing level is presented. At the circuit implementation level, in order to minimize the effect of mismatches, techniques are employed such as the use of a common resistor string DAC for all the channels and the use of appropriate autozeroing.; Within each channel, the speed of an individual SC pipeline ADC is limited by the closed-loop settling time of the sample-and-hold (S/H) and interstage residue amplifiers. To address this issue, an analytical approach to the design of any single-stage op amp for maximum speed in a given CMOS technology is described in detail. For circuit realization, the op amp topology used is a simple and intrinsically fast, mostly-NMOS, fully-differential, non-folded cascode operational transconductance amplifier.; A prototype parallel pipeline array ADC consisting of a time-interleaved combination of four SC multistage pipelined ADC's was implemented in a 1-{dollar}mu{dollar}m CMOS technology and 8-bit resolution at a sample rate of 85 MS/s was obtained; this is the fastest 8-bit CMOS ADC reported to date. Signal-to-Noise-plus-Distortion was 41 dB for an input sinusoid of 40 MHz. (Abstract shortened by UMI.)...