| Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. Ideally, if all paths from input to output have equal delay, then the circuit's clock frequency is only limited by rise/fall times, clock skew, and the set-up and hold times of the storage elements. In practice, due to the above parameters plus some residual difference between shortest and longest path delays, the clock frequency can be increased by a factor of 2 to 3 using the best available design methods.;We present algorithms to automatically equalize delays in combinational logic circuits to achieve wave pipelining. The algorithms adjust gate speeds and insert a minimal number of active delay elements to balance input-to-output path lengths in a circuit. For both normal and wave-pipelined circuits, the algorithms also optimally minimize power under delay constraints.;We describe an LSI chip design that demonstrates the concept of wave pipelining. The circuit is a 63-bit population counter which is similar in structure to a slice of a multiplier. This circuit has been designed in current-mode logic (CML) with a nominal delay of 9.5 ns. Full tests of fabricated chips show that a wave pipeline period of 4.0 ns has been achieved. In contrast, the ordinary pipeline period is 10.25 ns. By using wave pipelining, the clock frequency has been increased by 2.5 times without using additional registers.;We derive and compare mathematical constraints on path length and clock frequency required by ordinary and wave pipelined clocking schemes. In addition, self-timing, retiming, and intentional clock skewing are discussed.;Some technologies have less data-dependency in propagation delay than others. Technologies with uniform delay benefit most from wave pipelining. Factors that cause data-dependent delays are presented. |
