Maximum Time Difference Pipelining Technique Practical Design

During these decades, the number of transistors integrated on a single die grows double times per 18 months following the Moore law. Transistor's switch speed increases as the feature sizes shrink. Meanwhile, the clock rate of an integrated system is only as 10%-20% as the switch speed. This indicates a potential capability for much higher speed operation can get by using some advanced design technology. To minimize the speed gap between a signal gate and a circuit and thus to allow for maximal rate operation of the circuit, the technique of wave pipelining is proposed.Wave pipelining is a timing methodology used in digital systems to achieve maximal rate operation. The maximum clock frequency of a wave pipelined circuit is determined by the maximum difference between path delays in a stage, [35]. Thus, the smaller the maximum path delay difference, the greater the clock frequency at which the wave pipelined circuit can validly operate. Wave pipelining is a design technique, which can approach the system's clock frequency to switch speed offered by manufacture technology.Previous work on wave pipelining has focused on theoretically analysis of circuit's timing constraint condition, balancing a circuit by inserting delay cells to minimize the maximum path delay difference, and design an experience wave pipelined circuit. The work in this thesis concentrated on implementing wave pipelining. The main topic covered in this thesis was to simplify the design complexity of a wave pipelined system and to reduce the path delay difference considering input signals.For design methodology, design reused technique was first used to construct a wave pipelined circuit. The timing constraint conditions of wave pipelined circuits with macro cells have been discussed, and the validity of this method has also been discussed.To design a wave pipelined circuit, paths delay balancing is needed, but it is not needed for a conventional design. For fear to piling additional work on designer an EDA tool named WP-SP&R has been developed to be used to analyze circuits path delay and to minimize the path delay difference. A new kind of directed acyclic graph, which is called IORG(input output reverse graphic) was proposed to present circuit. IOGR can describe timing relationship between the inputs of a cell easily...